syn-fifo-verilog
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:98KB
下载次数:175
上传日期:2009-12-11 14:38:37
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说明: 用verilog语言写的同步FIFO设计源代码。
(The source codes for syn-fifo using verilog language.)
文件列表:
fifo_syn (0, 2008-07-26)
fifo_syn\fifo_syn_flag.v (1629, 2008-07-20)
fifo_syn\fifo_syn_ram.v (720, 2008-07-20)
fifo_syn\fifo_syn_rdaddr_gen.v (716, 2008-07-20)
fifo_syn\fifo_syn_top.v (1223, 2008-07-17)
fifo_syn\fifo_syn_wraddr_gen.v (732, 2008-07-20)
fifo_syn\fifo_top_tb.v (1195, 2008-07-26)
fifo_syn\同步FIFO设计.doc (77312, 2008-07-13)
fifo_syn\nLint.rc (4167, 2009-12-04)
fifo_syn\nLint.ds (16, 2009-12-04)
fifo_syn\.fifo_top_tb.v.swp (12288, 2009-12-10)
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