FPGA_Clk
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1432KB
下载次数：87
上传日期：2009-12-27 00:28:58
上 传 者：
icemoon1987
说明： 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。
使用计时器的方式产生时钟波形。
提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。
(Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.)
文件列表:
FPGA_Clk\db\add_sub_8rh.tdf (3060, 2009-07-28)
FPGA_Clk\db\altsyncram_kso3.tdf (7135, 2009-08-23)
FPGA_Clk\db\altsyncram_qso3.tdf (11447, 2009-08-23)
FPGA_Clk\db\cmpr_j4c.tdf (1590, 2009-08-23)
FPGA_Clk\db\cmpr_l4c.tdf (1756, 2009-08-23)
FPGA_Clk\db\cmpr_n4c.tdf (1912, 2009-08-23)
FPGA_Clk\db\cntr_a4i.tdf (4248, 2009-08-23)
FPGA_Clk\db\cntr_c4i.tdf (4248, 2009-08-23)
FPGA_Clk\db\cntr_cti.tdf (4897, 2009-08-23)
FPGA_Clk\db\cntr_iti.tdf (5130, 2009-08-23)
FPGA_Clk\db\cntr_p2i.tdf (3785, 2009-08-23)
FPGA_Clk\db\cntr_umi.tdf (3315, 2009-08-23)
FPGA_Clk\db\decode_9jf.tdf (1559, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(0).cnf.cdb (1801, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(0).cnf.hdb (679, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(1).cnf.cdb (7026, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(1).cnf.hdb (3021, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(10).cnf.cdb (1333, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(10).cnf.hdb (799, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(11).cnf.cdb (904, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(11).cnf.hdb (1097, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(12).cnf.cdb (1556, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(12).cnf.hdb (1466, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(13).cnf.cdb (2312, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(13).cnf.hdb (680, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(14).cnf.cdb (10976, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(14).cnf.hdb (3102, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(15).cnf.cdb (2573, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(15).cnf.hdb (690, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(16).cnf.cdb (1360, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(16).cnf.hdb (768, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(17).cnf.cdb (1409, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(17).cnf.hdb (769, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(18).cnf.cdb (4505, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(18).cnf.hdb (1149, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(19).cnf.cdb (1538, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(19).cnf.hdb (545, 2009-08-23)
FPGA_Clk\db\FPGA_Clk.(2).cnf.cdb (3017, 2009-07-28)
FPGA_Clk\db\FPGA_Clk.(2).cnf.hdb (1829, 2009-07-28)
FPGA_Clk\db\FPGA_Clk.(20).cnf.cdb (2264, 2009-08-23)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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