uart
所属分类：串口编程
开发工具：VHDL
文件大小：884KB
下载次数：16
上传日期：2010-01-02 01:15:04
上 传 者：
FightJun
说明： 程序说明:
本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。
目录说明:
工程在\project文件夹里面
源文件和管脚分配在\rtl文件夹里面
下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。
(Procedure Note: The experimental control development board above the serial port to communicate with the PC machine, and the serial wizard inside the display characters. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.)
文件列表:
s10_uart\introduc.txt (235, 2006-11-10)
s10_uart\project\bitgen.ut (470, 2006-04-24)
s10_uart\project\core.tpl (1356, 2006-04-24)
s10_uart\project\device_usage_statistics.html (21677, 2009-06-22)
s10_uart\project\div.cmd_log (55, 2006-04-24)
s10_uart\project\div.lso (6, 2006-04-24)
s10_uart\project\div.ngc (6477, 2006-04-24)
s10_uart\project\div.ngr (3836, 2006-04-24)
s10_uart\project\div.prj (22, 2006-04-24)
s10_uart\project\div.spl (78, 2006-04-24)
s10_uart\project\div.stx (0, 2006-04-24)
s10_uart\project\div.sym (524, 2006-04-24)
s10_uart\project\div.syr (11165, 2006-04-24)
s10_uart\project\div.v (805, 2006-04-24)
s10_uart\project\div_summary.html (3056, 2006-04-24)
s10_uart\project\div_vhdl.prj (0, 2006-04-24)
s10_uart\project\filter.spl (86, 2006-04-24)
s10_uart\project\filter.sym (655, 2006-04-24)
s10_uart\project\filter.v (819, 2006-04-24)
s10_uart\project\project.dhp (4888, 2006-10-11)
s10_uart\project\project.ise (309112, 2009-06-22)
s10_uart\project\project.ise_ISE_Backup (309112, 2009-06-22)
s10_uart\project\project.ntrc_log (110, 2009-06-22)
s10_uart\project\project.restore (53862, 2009-06-22)
s10_uart\project\project_ise9migration.zip (395112, 2009-06-22)
s10_uart\project\rcvr.v (2512, 2005-06-07)
s10_uart\project\templates\coregen.xml (1277, 2009-06-22)
s10_uart\project\timing.twr (2276, 2009-06-22)
s10_uart\project\top.bgn (5164, 2009-06-22)
s10_uart\project\top.bit (212461, 2009-06-22)
s10_uart\project\top.bld (931, 2009-06-22)
s10_uart\project\top.cel (0, 2006-04-25)
s10_uart\project\top.cmd_log (1668, 2009-06-22)
s10_uart\project\top.drc (38, 2009-06-22)
s10_uart\project\top.jhd (164, 2009-06-22)
s10_uart\project\top.lfp (163, 2006-04-24)
s10_uart\project\top.lso (6, 2006-04-24)
s10_uart\project\top.mrp (8577, 2006-04-24)
s10_uart\project\top.ncd (46989, 2009-06-22)
s10_uart\project\top.ngc (52294, 2009-06-22)
... ...
The following files were generated for in directory
D:\xuexi\dianzi\sp\3s400\examples\s6_rs232\project:
uart_rom.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
uart_rom.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
uart_rom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
uart_rom.sym:
Please see the core data sheet.
uart_rom.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
uart_rom.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
uart_rom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
uart_rom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
uart_rom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
uart_rom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
uart_rom_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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