文件列表:

nios_lcd_3c120\altpllpll.ppf (419, 2008-11-07)
nios_lcd_3c120\altpllpll.qip (363, 2008-11-07)
nios_lcd_3c120\altpllpll.v (15550, 2008-11-07)
nios_lcd_3c120\altpllpll_bb.v (11772, 2008-11-07)
nios_lcd_3c120\alt_mem_phy_defines.v (5281, 2008-11-07)
nios_lcd_3c120\alt_mem_phy_sequencer.vhd (634688, 2008-11-07)
nios_lcd_3c120\auk_ddr_hp_controller.ocp (488, 2008-11-07)
nios_lcd_3c120\auk_ddr_hp_controller.vhd (296944, 2008-11-07)
nios_lcd_3c120\board_support.tcl (53682, 2008-11-07)
nios_lcd_3c120\button_pio.v (4151, 2008-11-07)
nios_lcd_3c120\common_hpddr_setting.tcl (174, 2008-11-07)
nios_lcd_3c120\common_kits_setting.tcl (1210, 2008-11-07)
nios_lcd_3c120\common_nios2_setting.tcl (982, 2008-11-07)
nios_lcd_3c120\common_timequest_setting.tcl (204, 2008-11-07)
nios_lcd_3c120\common_tse_setting.tcl (3154, 2008-11-07)
nios_lcd_3c120\cpu.ocp (840, 2008-11-07)
nios_lcd_3c120\cpu.sdc (3585, 2008-11-07)
nios_lcd_3c120\cpu.v (397944, 2008-11-07)
nios_lcd_3c120\cpu_bht_ram.mif (2126, 2008-11-07)
nios_lcd_3c120\cpu_dc_tag_ram.mif (12368, 2008-11-07)
nios_lcd_3c120\cpu_ddr_1_clock_bridge.v (12581, 2008-11-07)
nios_lcd_3c120\cpu_ddr_clock_bridge.v (12469, 2008-11-07)
nios_lcd_3c120\cpu_ic_tag_ram.mif (14416, 2008-11-07)
nios_lcd_3c120\cpu_jtag_debug_module_sysclk.v (6452, 2008-11-07)
nios_lcd_3c120\cpu_jtag_debug_module_tck.v (7668, 2008-11-07)
nios_lcd_3c120\cpu_jtag_debug_module_wrapper.v (9106, 2008-11-07)
nios_lcd_3c120\cpu_mult_cell.v (5978, 2008-11-07)
nios_lcd_3c120\cpu_ociram_default_contents.mif (5878, 2008-11-07)
nios_lcd_3c120\cpu_oci_test_bench.v (1294, 2008-11-07)
nios_lcd_3c120\cpu_rf_ram_a.mif (558, 2008-11-07)
nios_lcd_3c120\cpu_rf_ram_b.mif (558, 2008-11-07)
nios_lcd_3c120\cpu_test_bench.v (38536, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.done (25, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.fit.smsg (507, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.fit.summary (669, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.jdi (10126, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.map.smsg (2147, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.map.summary (516, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.pin (91079, 2008-11-07)
nios_lcd_3c120\cycloneIII_3c120_niosII_video.qpf (910, 2008-11-07)
... ...

Overview: - This design is based on the Nios II/f core and provides a typical mix of peripherals and memories as well as a video pipeline. The SOPC Builder system provides an interface to each hardware component on the embedded evaluation kit board, such as DDR SDRAM, LEDs, RS-232 connector, and the Ethernet MAC/10/100 PHY as well as the 800 x 240 pixel RGB LCD. There is also a video pipeline which provides high bandwidth memory access that allows for flicker free display on the color LCD. - This is a list of the components available in the system along with a brief description: cpu Nios2/f pipeline_bridge_before_tristate_bridge flash_ssram_tristate_bridge ext_flash parallel flash ssram 1 MByte synchronous SRAM for board 3c25 ddr_sdram for board 3c25 ddr2_sdram for board 3c120 cpu_ddr_clock_bridge - These bridges are here for two reasons: 1) Clock cross between two components that are clocked at a different frequency. * sdhc_ddr_clock_bridge * tse_ddr_clock_bridge * tse_ssram_clock_bridge for board 3c25 2) To offset addresses so that the entire memory model is flat. (Every master sees every slave at the same address). * descriptor_offset_bridge - The triple speed Ethernet components (for board 3c25, those components are on slow_peripheral_bridge): * tse_mac * sgdma_tx * sgdma_rx * descriptor_memory - The Cyclone III 3c120 dev kit Max II interface component is used to access the Max II device on 3c120 developoment board, for reconfiguration purpose. Please refer to the readme file of the component for further detail. Components on the slow peripheral bridge ========================================= - Components listed here are partitioned off by the use of the slow_peripheral_bridge. This allows non-fmax critical components to be clocked at a slower clock rate to give better fitting for components that are fmax-critical. - The Bridge * slow_peripheral_bridge - The rest of the components on the slow_peripheral_bridge * sys_clk_timer * performance_counter * jtag_uart * sysid * pll * button_pio * led_pio * pio_id_eeprom_dat * pio_id_eeprom_scl used to access EEProm * remote_update for board 3c25 - The following components are used to communicate with the touch panel * touch_panel_spi * touch_panel_pen_irq_n - The sd card solution is provided under license agreement with El Camino (http://www.elcamino.de) * el_camino_sd_card_controller The video pipeline: =================== - The following i2c pins are used to configure the lcd panel for brightness and gamma curves * lcd_i2c_scl * lcd_i2c_en * lcd_i2c_sdat - The rest of the components that make up the video pipeline: * lcd_sgdma * lcd_ta_sgdma_to_fifo * lcd_pixel_fifo * lcd_ta_fifo_to_dfa * lcd_***_to_32_bits_dfa * lcd_pixel_converter * lcd_32_to_8_bits_dfa * lcd_sync_generator Further Notes: ============== - For board 3c25, the design contains a PLL that produces a phase-shifted clock to feed the SSRAM. The phase shift is board-dependent, and may be different if this design is retargeted to a different board. - This Quartus II project contains assignments that match the port names produced by SOPC Builder. If you add or modify SOPC Builder components, the pin assignments may no longer be valid. To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor". - This design contains the DDR memory components. Any design containing these cores must be re-generated in SOPC Builder before to re-compiling it in Quartus, if it the installation path to the Altera toolchain has changed since it was last generated. This is because these cores make use of RTL libraries that are referenced using absolute paths. The re-generation process will update these absolute paths. Attempting to recompile in Quartus II without regenerating will result in an error of the following form during Quartus II Analysis and Synthesis: Error: Node instance "ddr_control" instantiates undefined entity "auk_ddr_controller" - For board 3c25, DDR memory is the main memory of the system, however SSRAM has a faster access speed (when using the same clock frequencies). - For board 3c120, dual bank DDR memory is used as program and data memory - The current version of the Nios II EDS hardware design example uses an HDL file as the top level of the design hierarchy. If you would like to use a schematic-based top level instead (BDF), follow the steps listed below. 1) In the Quartus II software, open the top-level HDL file (.v or .vhd) for the design. 2) Create a symbol for the HDL file by clicking File -> Create/Update -> Create Symbol Files for Current File 3) Create a new BDF file by clicking File -> New -> Block Diagram/Schematic File. 4) Instantiate the symbol in the BDF by double-clicking in the empty space of the BDF file and selecting "Project -> " 5) Instantiate pins in the BDF by double-clicking empty space, then typing "input", "output", or "bidir". 6) Rename the pins and connect them to the appropriate ports on the symbol. 7) Save the BDF as a unique filename. 8) Set the BDF as your top level entity by clicking: Project -> Set as Top-Level Entity 9) Recompile the Quartus II project. - For board 3c120, SLS SD Host Controller is used to access the sd card content. To customize the design like removing the IP core, you need to disable the component in SOPC Builder and re-generate the design. Then remove the corresponding pins in the top-level HDL file and run Quartus II compilation again. - To compile this software in Nios II IDE, you need to append this Project directory or the directory that contains the altera_avalon_sd_mmc_spi component to the "SOPC_BUILDER_PATH" Environment Variable, so that the build tools will be able to locate the drivers for the SD controller. For more information and details, refer to the Nios II Embedded Design Suite Release Note.

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