说明：  提高设计的工作频率 通过附加约束可以控制逻辑的综合、映射、布局和布线，以减小逻辑和布线延时，从而提高工作频率。 获得正确的时序分析报告 FPGA设计平台包含静态时序分析工具，可以获得映射或布局布线后的时序分析报告，从而对设计的性能做出评估。 静态时序分析工具以约束作为判断时序是否满足设计要求的标准。
(Improve the design of the operating frequency can be controlled by additional constraints logic synthesis, map, layout and routing, to reduce the logic and routing delay, thereby increasing the operating frequency. Obtain the correct timing analysis of FPGA design platform that contains static timing analysis tool, map, or get post-layout timing analysis report, and thus to assess the performance of the design. Static timing analysis tool to determine timing constraints as the design meets the required standards.)