LUdecompose

所属分类:VHDL/FPGA/Verilog
开发工具:Windows_Unix
文件大小:10587KB
下载次数:106
上传日期:2010-01-06 17:23:33
上 传 者jlwzyang
说明:  基于verilog的LU分解,本文件包括详细的程序代码,运行文件,以及详细的文档
(LU decompose based on verilog)

文件列表:
LU分解\lu_decomposition\blk_mem_gen_ds512.pdf (2107313, 2008-05-28)
LU分解\lu_decomposition\blk_mem_gen_release_notes.txt (4492, 2008-05-28)
LU分解\lu_decomposition\block_ram.asy (699, 2008-05-25)
LU分解\lu_decomposition\block_ram.ngc (22255, 2008-05-25)
LU分解\lu_decomposition\block_ram.sym (1229, 2008-05-25)
LU分解\lu_decomposition\block_ram.v (4550, 2008-05-25)
LU分解\lu_decomposition\block_ram.veo (3117, 2008-05-25)
LU分解\lu_decomposition\block_ram.vhd (5126, 2008-05-25)
LU分解\lu_decomposition\block_ram.vho (3645, 2008-05-25)
LU分解\lu_decomposition\block_ram.xco (2121, 2008-05-25)
LU分解\lu_decomposition\block_ram_blk_mem_gen_v2_4_xst_1.lso (18, 2008-05-25)
LU分解\lu_decomposition\block_ram_blk_mem_gen_v2_4_xst_1_vhdl.prj (2425, 2008-05-25)
LU分解\lu_decomposition\block_ram_flist.txt (242, 2008-05-25)
LU分解\lu_decomposition\block_ram_summary.html (2316, 2008-05-26)
LU分解\lu_decomposition\block_ram_xmdf.tcl (3226, 2008-05-25)
LU分解\lu_decomposition\divider.asy (437, 2008-05-25)
LU分解\lu_decomposition\divider.sym (810, 2008-05-25)
LU分解\lu_decomposition\divider.v (476734, 2008-05-25)
LU分解\lu_decomposition\divider.veo (3021, 2008-05-25)
LU分解\lu_decomposition\divider.vhd (4738, 2008-05-25)
LU分解\lu_decomposition\divider.vho (3457, 2008-05-25)
LU分解\lu_decomposition\divider.xco (1793, 2008-05-25)
LU分解\lu_decomposition\divider_flist.txt (177, 2008-05-25)
LU分解\lu_decomposition\divider_xmdf.tcl (3000, 2008-05-25)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\hdllib.ref (1374, 2008-05-28)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_f_d_e\mingw\_f_d_e.obj (32375, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_f_d_e\_f_d_e.h (1040, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_f_d_r_s\mingw\_f_d_r_s.obj (33912, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_f_d_r_s\_f_d_r_s.h (1090, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_g_n_d\mingw\_g_n_d.obj (9989, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_g_n_d\_g_n_d.h (973, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_i_n_v\mingw\_i_n_v.obj (16967, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_i_n_v\_i_n_v.h (973, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_l_u_t1\mingw\_l_u_t1.obj (18893, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_l_u_t1\_l_u_t1.h (1004, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_l_u_t2\mingw\_l_u_t2.obj (23320, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_l_u_t2\_l_u_t2.h (1031, 2008-05-26)
LU分解\lu_decomposition\isim\unisim_ver.auxlib\_l_u_t3\mingw\_l_u_t3.obj (42639, 2008-05-26)
... ...

The following files were generated for 'sub' in directory D:\Program Files\ISE9.2i\My_program\lu_decomposition: sub.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. sub.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. sub.sym: Please see the core data sheet. sub.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. sub.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. sub.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. sub.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. sub.xco: CORE Generator input file containing the parameters used to regenerate a core. sub_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. sub_readme.txt: Text file indicating the files generated and how they are used. sub_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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