AES_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：78KB
下载次数：312
上传日期：2010-01-08 13:19:32
上 传 者：
carol_lrl
说明： AES 128bit数据,128bit密钥加解密的verilog语言实现
(AES 128bit data, 128bit key encryption and decryption of the verilog language implementation)
文件列表:
aes_core\vim_session.vim (5465, 2002-11-09)
aes_core\bench\CVS\Entries (14, 2004-03-14)
aes_core\bench\CVS\Repository (15, 2004-03-14)
aes_core\bench\CVS\Root (14, 2004-03-14)
aes_core\bench\CVS (0, 2005-04-28)
aes_core\bench\verilog\test_bench_top.v (37033, 2002-11-13)
aes_core\bench\verilog\CVS\Entries (51, 2004-03-14)
aes_core\bench\verilog\CVS\Repository (23, 2004-03-14)
aes_core\bench\verilog\CVS\Root (14, 2004-03-14)
aes_core\bench\verilog\CVS (0, 2005-04-28)
aes_core\bench\verilog (0, 2005-04-28)
aes_core\bench (0, 2005-04-28)
aes_core\CVS\Entries (104, 2004-03-14)
aes_core\CVS\Repository (9, 2004-03-14)
aes_core\CVS\Root (14, 2004-03-14)
aes_core\CVS (0, 2005-04-28)
aes_core\doc\aes.pdf (73346, 2002-11-13)
aes_core\doc\CVS\Entries (45, 2004-03-14)
aes_core\doc\CVS\Repository (13, 2004-03-14)
aes_core\doc\CVS\Root (14, 2004-03-14)
aes_core\doc\CVS (0, 2005-04-28)
aes_core\doc (0, 2005-04-28)
aes_core\rtl\CVS\Entries (14, 2004-03-14)
aes_core\rtl\CVS\Repository (13, 2004-03-14)
aes_core\rtl\CVS\Root (14, 2004-03-14)
aes_core\rtl\CVS (0, 2005-04-28)
aes_core\rtl\verilog\aes_cipher_top.v (10230, 2002-11-09)
aes_core\rtl\verilog\aes_inv_cipher_top.v (11671, 2002-11-09)
aes_core\rtl\verilog\aes_inv_sbox.v (8257, 2002-11-09)
aes_core\rtl\verilog\aes_key_expand_128.v (3914, 2002-11-09)
aes_core\rtl\verilog\aes_rcon.v (3773, 2002-11-09)
aes_core\rtl\verilog\aes_sbox.v (8246, 2002-11-09)
aes_core\rtl\verilog\timescale.v (22, 2002-11-13)
aes_core\rtl\verilog\CVS\Entries (358, 2004-03-14)
aes_core\rtl\verilog\CVS\Repository (21, 2004-03-14)
aes_core\rtl\verilog\CVS\Root (14, 2004-03-14)
aes_core\rtl\verilog\CVS (0, 2005-04-28)
aes_core\rtl\verilog (0, 2005-04-28)
aes_core\rtl (0, 2005-04-28)
aes_core\sim\CVS\Entries (14, 2004-03-14)
... ...
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