说明：  FPGA设计时,常遇到多个时钟一起工作的情况, 这时就要考虑时钟域的问题,以及不同时钟域间的通信.此文详细介绍了跨时钟设计的相关问题.
(FPGA design, often encounter a number of clock to work together, when we must consider the clock domains, as well as communication between different clock domains. This article details the cross-clock design related issues.)