EDA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2328KB
下载次数：12
上传日期：2010-01-14 17:12:42
上 传 者：
Cristina_wd
说明： 课程实验，VHDL语言实现半加器全加器，频率计等，共四个
(eda)
文件列表:
实验一\db\full_adder.(0).cnf.cdb (642, 2009-09-24)
实验一\db\full_adder.(0).cnf.hdb (399, 2009-09-24)
实验一\db\full_adder.(1).cnf.cdb (830, 2009-09-24)
实验一\db\full_adder.(1).cnf.hdb (593, 2009-09-24)
实验一\db\full_adder.asm.qmsg (1982, 2009-09-24)
实验一\db\full_adder.asm_labs.ddb (455813, 2009-09-24)
实验一\db\full_adder.cbx.xml (92, 2009-09-24)
实验一\db\full_adder.cmp.bpm (431, 2009-09-24)
实验一\db\full_adder.cmp.cdb (2267, 2009-09-24)
实验一\db\full_adder.cmp.ecobp (28, 2009-09-24)
实验一\db\full_adder.cmp.hdb (6182, 2009-09-24)
实验一\db\full_adder.cmp.logdb (4, 2009-09-24)
实验一\db\full_adder.cmp.rdb (19962, 2009-09-24)
实验一\db\full_adder.cmp.tdb (1261, 2009-09-24)
实验一\db\full_adder.cmp0.ddb (45786, 2009-09-24)
实验一\db\full_adder.cmp_bb.cdb (1489, 2009-09-24)
实验一\db\full_adder.cmp_bb.hdb (6119, 2009-09-24)
实验一\db\full_adder.cmp_bb.logdb (4, 2009-09-24)
实验一\db\full_adder.cmp_bb.rcf (642, 2009-09-24)
实验一\db\full_adder.dbp (0, 2009-09-24)
实验一\db\full_adder.db_info (136, 2009-09-24)
实验一\db\full_adder.eco.cdb (161, 2009-09-28)
实验一\db\full_adder.eds_overflow (3, 2009-09-24)
实验一\db\full_adder.fit.qmsg (11981, 2009-09-24)
实验一\db\full_adder.fnsim.hdb (6045, 2009-09-24)
实验一\db\full_adder.fnsim.qmsg (3654, 2009-09-24)
实验一\db\full_adder.hier_info (618, 2009-09-24)
实验一\db\full_adder.hif (809, 2009-09-24)
实验一\db\full_adder.map.bpm (431, 2009-09-24)
实验一\db\full_adder.map.cdb (1016, 2009-09-24)
实验一\db\full_adder.map.ecobp (28, 2009-09-24)
实验一\db\full_adder.map.hdb (6018, 2009-09-24)
实验一\db\full_adder.map.logdb (4, 2009-09-24)
实验一\db\full_adder.map.qmsg (4120, 2009-09-24)
实验一\db\full_adder.map_bb.cdb (891, 2009-09-24)
实验一\db\full_adder.map_bb.hdb (5981, 2009-09-24)
实验一\db\full_adder.map_bb.logdb (4, 2009-09-24)
实验一\db\full_adder.merge.qmsg (2068, 2009-09-24)
实验一\db\full_adder.pre_map.cdb (1031, 2009-09-24)
实验一\db\full_adder.pre_map.hdb (6304, 2009-09-24)
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