文件列表:

61i_radix2_xfft1024_v2_0_ver_ise\61i_radix2_xfft1024_v2_0_ver.npl (1826, 2003-12-03)
61i_radix2_xfft1024_v2_0_ver_ise\design_top.ucf (149, 2003-11-26)
61i_radix2_xfft1024_v2_0_ver_ise\design_top.v (4198, 2003-12-03)
61i_radix2_xfft1024_v2_0_ver_ise\design_top_dc_input_tb.tf (2436, 2003-10-30)
61i_radix2_xfft1024_v2_0_ver_ise\design_top_tb.tf (3698, 2003-12-03)
61i_radix2_xfft1024_v2_0_ver_ise\design_top_tb_tf.udo (2929, 2003-12-03)
61i_radix2_xfft1024_v2_0_ver_ise\my_radix2_xfft1024.edn (1413042, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise\my_radix2_xfft1024.v (4656, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise\my_radix2_xfft1024.veo (3360, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise\my_radix2_xfft1024.xco (7974, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise\my_radix2_xfft1024_fft20_flow_control_c_1.ngc (50192, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise\sine_9_375mhz.dat (71043, 2003-12-03)
61i_radix2_xfft1024_v2_0_ver_ise\wrapped_fft20_sin_cos_TRIG_ROM.mif (19456, 2003-11-21)
61i_radix2_xfft1024_v2_0_ver_ise (0, 2003-12-03)

============================================================= VERSION 2.0 DECEMBER 03, 2003 ============================================================= The files in this example are only intended to be used as a reference for those who are familiar with Coregen and the other Xilinx tools. For more thorough documentation, please see the Coregen User Guide: http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm ============================================================= ============================================================= FILES INCLUDED IN ZIP ============================================================= readme.txt - This readme file. my_radix2_xfft1024.xco - Core parameter file my_radix2_xfft1024.veo - Core Verilog instantiation template my_radix2_xfft1024.v - Core Verilog simulation file (only for simulation) wrapped_fft20_sin_cos_TRIG_ROM.mif - - Core initialization file (only for simulatoin) my_radix2_xfft1024.edn - Core EIDF netlist (only for implementation) my_radix2_xfft1024_fft20_flow_control_c_1.ngc - Core EIDF netlist (only for implementation) design_top.ucf - contrsaints file (only for implementation) design_top.v - Verilog toplevel design_top_dc_input_tb.tf - Alternate Verilog testbench design_top_tb.tf - Verilog testbench sine_9_375mhz.dat - Verilog testbench stimulas design_top_tb_tf.udo - ModelSim Do file that will format the output waveforms Project Navigaor Only Files: 61i_radix2_xfft1024_v2_0_ver_ise.npl - Project Navigator project file ============================================================= SIMULATION ============================================================= -------------------- MODELSIM ------------------------ * Before the simulation can be run, the XilinxCoreLib library needs to be compiled. Also, it has to have been compiled after the installation of 6.1i or a later IP UPDATE. If this has not been done, please install the latest IP UPDATE. Then follow Xilinx Solution 2561. * If using ModelSim XE (Xilinx Edition), the models are precompiled. Go to the following site and make sure that the latest models have been downloaded: http://support.xilinx.com/support/mxelibs/index.htm Again, 6.1i or later is needed to run this simulation. -------------------- ISE PROJECT ------------------------ Steps to Simulate: 1.Unzip the downloaded to a user chosen directory 2.Open ISE and select "Open project" under the file menu 3.Select the example_name.npl file found in the previously unzipped directory 4.To view individual items of code, double click on the file in "Sources in Project" window 5.To functionally simulate the core, highlight the testbench, and double click the "Simulate Post-Translate Verilog model" in the "Processes for Current Source" window ----------------- OTHER SIMULATORS ------------------- The exact commands for other simulators are not provided in this file. Please see the following site for tutorials on using other simulators: http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm ============================================================= ISE - Using Coregen ============================================================= To use Coregen in ISE, please refer to the following document: ftp://ftp.xilinx.com/pub/documentation/misc/coregen_ise.pdf

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