array(4) { [0]=> string(27) "SystemVerilog Event Regions" [1]=> string(33) " Race Avoidance & Guidelines .pdf" [2]=> string(7) " 395886" [3]=> string(21) " 2009-10-25 11:59:5 " } SystemVerilogEventRegionsRaceAvoidanceGuidelines 联合开发网 - pudn.com
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SystemVerilogEventRegionsRaceAvoidanceGuidelines
paper systemverilog verification abv The Common 
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所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：348KB
下载次数：7
上传日期：2010-01-19 22:17:49
上 传 者：bbsky
说明：  The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.
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