7to1lvds
所属分类：汇编语言
开发工具：VHDL
文件大小：19KB
下载次数：25
上传日期：2010-01-27 15:23:37
上 传 者：
andy840124
说明： spi——HOST可以实现SPI的HOST
7:1 LVDS
(this IS 7:1 LVDS transfer and SPI_host control )
文件列表:
7to1lvds\asyn_fifo.v (4552, 2008-09-04)
7to1lvds\gray_counter.v (1286, 2008-09-04)
7to1lvds\lvds_7to1_rx_clksyn.v (6127, 2008-12-01)
7to1lvds\lvds_7to1_rx_logic.v (9936, 2008-12-01)
7to1lvds\lvds_7to1_rx_top.v (4071, 2008-12-01)
7to1lvds\lvds_7to1_tx_logic.v (7005, 2008-12-01)
7to1lvds\lvds_7to1_tx_top.v (7416, 2008-12-01)
7to1lvds\sb_ice_syn.v (92068, 2008-11-17)
7to1lvds\tb_lvds_7to1_tx_rx_top.v (3233, 2008-12-01)
7to1lvds\wave_top.do (2019, 2008-12-01)
7to1lvds (0, 2010-01-27)
24-bpp 7:1 LVDS Transmitter & Receiver Nov 30, 2008
=====================================================
Transmitter:
a) Transmiter Verilog files : lvds_7to1_tx_top.v lvds_7to1_tx_logic.v asyn_fifo.v gray_counter.v
b) Transmiter Verilog files : lvds_7to1_rx_top.v lvds_7to1_rx_logic.v lvds_7to1_rx_clksyn.v asyn_fifo.v gray_counter.v
b) Testbench files : tb_lvds_7to1_tx_rx_top.v sb_ice_syn.v
c) To run modelsim simulation
i) vlog lvds_7to1_tx_top.v lvds_7to1_tx_logic.v asyn_fifo.v gray_counter.v
ii) vlog lvds_7to1_rx_top.v lvds_7to1_rx_logic.v lvds_7to1_rx_clksyn.v asyn_fifo.v gray_counter.v
iii) vlib LIB
iv) vlog -work ./LIB sb_ice_syn.v
v) vlog tb_lvds_7to1_tx_rx_top.v
vi) vsim -L ./LIB tb
vii) do wave_top.do
viii) run 100us
ix) Check rx_err signal : 1 = error, 0 = no error
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