dianzizhong
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：538KB
下载次数：1429
上传日期：2005-08-03 16:44:14
上 传 者：
amgo
说明： 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!
(This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!)
文件列表:
clk\cnt60a.vhd (1563, 2005-06-05)
clk\cnt_24.qpf (941, 2005-06-05)
clk\cnt_24.qsf (2395, 2005-06-05)
clk\db\clock.hif (11564, 2005-06-05)
clk\db\cnt_24.db_info (135, 2005-06-05)
clk\db\cnt_24.fit.qmsg (6867, 2005-06-05)
clk\db\cnt_24.(0).cnf.cdb (5821, 2005-06-05)
clk\db\cnt_24.(0).cnf.hdb (793, 2005-06-05)
clk\db\cnt_24.asm.qmsg (1112, 2005-06-05)
clk\db\clock.db_info (135, 2005-06-05)
clk\db\cnt_24_cmp.qrpt (0, 2005-06-05)
clk\db\cnt_24.cbx.xml (196, 2005-06-05)
clk\db\cnt_24.hif (11289, 2005-06-05)
clk\db\cnt_24.tan.qmsg (66597, 2005-06-05)
clk\db\cnt_24.map.qmsg (7877, 2005-06-05)
clk\db\cnt_24.hier_info (5622, 2005-06-05)
clk\db\cnt_24.rtlv_sg_swap.cdb (633, 2005-06-05)
clk\db\cnt_24.pre_map.hdb (9070, 2005-06-05)
clk\db\cnt_24.cmp.hdb (13208, 2005-06-05)
clk\db\cnt_24.(9).cnf.cdb (1257, 2005-06-05)
clk\db\cnt_24.(9).cnf.hdb (858, 2005-06-05)
clk\db\cnt_24.rtlv_sg.cdb (7375, 2005-06-05)
clk\db\clock.psp (0, 2005-06-05)
clk\db\cnt_24.psp (0, 2005-06-05)
clk\db\cnt_24.pre_map.cdb (8181, 2005-06-05)
clk\db\cnt_24.map.cdb (9349, 2005-06-05)
clk\db\cnt_24.map.hdb (13080, 2005-06-05)
clk\db\cnt_24.syn_hier_info (0, 2005-06-05)
clk\db\cnt_24.rtlv.hdb (9038, 2005-06-05)
clk\db\cnt_24.sgdiff.cdb (8989, 2005-06-05)
clk\db\clock.map.qmsg (8080, 2005-06-05)
clk\db\cnt_24.(10).cnf.cdb (4533, 2005-06-05)
clk\db\cnt_24.(10).cnf.hdb (571, 2005-06-05)
clk\db\cnt_24.sgdiff.hdb (19475, 2005-06-05)
clk\db\cnt_24.eco.cdb (140, 2005-06-05)
clk\db\cnt_24.cmp.tdb (21997, 2005-06-05)
clk\db\cnt_24.sld_design_entry_dsc.sci (134, 2005-06-05)
clk\db\cnt_24.cmp.rdb (19210, 2005-06-05)
clk\db\cnt_24.cmp0.ddb (6825, 2005-06-05)
clk\db\cnt_24.cmp.cdb (27604, 2005-06-05)
... ...
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