fir
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3245KB
下载次数：113
上传日期：2010-02-07 14:20:47
上 传 者：
wakao
说明： 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。
(Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.)
文件列表:
fir实现程序\fir8\chaolu.cdc (564, 2009-11-28)
fir实现程序\fir8\coregen.cgp (520, 2009-11-28)
fir实现程序\fir8\coregen.log (0, 2009-11-28)
fir实现程序\fir8\coregen.rsp (275, 2009-11-28)
fir实现程序\fir8\dds1.asy (260, 2009-11-28)
fir实现程序\fir8\dds1.cdc (564, 2009-11-28)
fir实现程序\fir8\dds1.ngc (98872, 2009-11-28)
fir实现程序\fir8\dds1.sym (487, 2009-11-28)
fir实现程序\fir8\dds1.v (106724, 2009-11-28)
fir实现程序\fir8\dds1.veo (2960, 2009-11-28)
fir实现程序\fir8\dds1.vhd (4294, 2009-11-28)
fir实现程序\fir8\dds1.vho (3340, 2009-11-28)
fir实现程序\fir8\dds1.xco (2535, 2009-11-28)
fir实现程序\fir8\dds1_dds_compiler_v2_1_xst_1.ngc_xst.xrpt (5771, 2009-11-28)
fir实现程序\fir8\dds1_flist.txt (187, 2009-11-28)
fir实现程序\fir8\dds1_xmdf.tcl (3146, 2009-11-28)
fir实现程序\fir8\dds2.asy (260, 2009-11-28)
fir实现程序\fir8\dds2.ngc (98865, 2009-11-28)
fir实现程序\fir8\dds2.sym (487, 2009-11-28)
fir实现程序\fir8\dds2.v (106717, 2009-11-28)
fir实现程序\fir8\dds2.veo (2960, 2009-11-28)
fir实现程序\fir8\dds2.vhd (4285, 2009-11-28)
fir实现程序\fir8\dds2.vho (3340, 2009-11-28)
fir实现程序\fir8\dds2.xco (2537, 2009-11-28)
fir实现程序\fir8\dds2_dds_compiler_v2_1_xst_1.ngc_xst.xrpt (5771, 2009-11-28)
fir实现程序\fir8\dds2_flist.txt (187, 2009-11-28)
fir实现程序\fir8\dds2_xmdf.tcl (3146, 2009-11-28)
fir实现程序\fir8\device_usage_statistics.html (72234, 2009-12-05)
fir实现程序\fir8\fir8.ise (348676, 2009-12-05)
fir实现程序\fir8\fir8.ntrc_log (395, 2009-12-05)
fir实现程序\fir8\fir8.restore (65611, 2009-12-05)
fir实现程序\fir8\fir8_xdb\cst.xbcd (6209, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\version (144, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\__OBJSTORE__\ExpandedNetlistEngine\Colors (27, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\__OBJSTORE__\ExpandedNetlistEngine\Colors_StrTbl (27, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\__OBJSTORE__\ExpandedNetlistEngine\Groups (29, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\__OBJSTORE__\ExpandedNetlistEngine\Groups_StrTbl (10, 2009-12-05)
fir实现程序\fir8\fir8_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject (201, 2009-12-05)
... ...
The following files were generated for 'hj' in directory
G:\fir8\fir8:
hj.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
hj.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
hj.sym:
Please see the core data sheet.
hj.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
hj.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
hj.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
hj.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
hj.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
hj_dds_compiler_v2_1_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
hj_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
hj_readme.txt:
Text file indicating the files generated and how they are used.
hj_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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