12334
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：233KB
下载次数：6
上传日期：2010-02-18 02:09:12
上 传 者：
mjm614
说明： verilog HDL reference
文件列表:
calc1_black_box\alu_input_stage\_primary.vhd (814, 2009-10-17)
calc1_black_box\alu_input_stage\_primary.dbs (2340, 2009-10-17)
calc1_black_box\alu_input_stage\_primary.dat (1224, 2009-10-17)
calc1_black_box\calc1_top\_primary.dat (7316, 2009-10-17)
calc1_black_box\calc1_top\_primary.vhd (1361, 2009-10-17)
calc1_black_box\calc1_top\_primary.dbs (21338, 2009-10-17)
calc1_black_box\priority\_primary.vhd (1091, 2009-10-17)
calc1_black_box\priority\_primary.dbs (9409, 2009-10-17)
calc1_black_box\priority\_primary.dat (4647, 2009-10-17)
calc1_black_box\alu_output_stage\_primary.dbs (3637, 2009-10-17)
calc1_black_box\alu_output_stage\_primary.vhd (1099, 2009-10-17)
calc1_black_box\alu_output_stage\_primary.dat (1917, 2009-10-17)
calc1_black_box\exdbin_mac\_primary.dat (94205, 2009-10-17)
calc1_black_box\exdbin_mac\_primary.vhd (418, 2009-10-17)
calc1_black_box\exdbin_mac\_primary.dbs (237175, 2009-10-17)
calc1_black_box\shifter\_primary.dat (148182, 2009-10-17)
calc1_black_box\shifter\_primary.vhd (412, 2009-10-17)
calc1_black_box\shifter\_primary.dbs (210719, 2009-10-17)
calc1_black_box\holdreg\_primary.vhd (656, 2009-10-17)
calc1_black_box\holdreg\_primary.dbs (2232, 2009-10-17)
calc1_black_box\holdreg\_primary.dat (1158, 2009-10-17)
calc1_black_box\mux_out\_primary.dat (600, 2009-10-17)
calc1_black_box\mux_out\_primary.dbs (1034, 2009-10-17)
calc1_black_box\mux_out\_primary.vhd (441, 2009-10-17)
calc1_black_box\calc1\_primary.vhd (1123, 2009-10-17)
calc1_black_box\calc1\_primary.dbs (2702, 2009-10-17)
calc1_black_box\calc1\_primary.dat (967, 2009-10-17)
calc1_black_box\_vmake (26, 2009-10-17)
calc1_black_box\_info (1423, 2009-10-17)
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