ddr2_controller

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:51KB
下载次数:390
上传日期:2010-02-23 09:16:50
上 传 者itman
说明:  DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.
(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)

文件列表:
ddr2_controller\dcm_0.v (3444, 2009-05-20)
ddr2_controller\ddr2_spartan3a1400abank1fg676.v (2695, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_addr_gen_0.v (4485, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_cal_ctl_0.v (4524, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_cal_top.v (1492, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_clk_dcm.v (2066, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_cmd_fsm_0.v (5350, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_cmp_data_0.v (3079, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_controller_0.v (39157, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_controller_iobs_0.v (5220, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_data_path_0.v (4613, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_data_path_iobs_0.v (3639, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_data_read_0.v (5571, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_data_read_controller_0.v (6846, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_data_write_0.v (4401, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_dqs_delay.v (2033, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_fifo_0_wr_en_0.v (1363, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_fifo_1_wr_en_0.v (1459, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_infrastructure.v (1446, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_infrastructure_iobs_0.v (2260, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_infrastructure_top_0.v (7345, 2009-05-20)
ddr2_controller\ddr2_spartan3a1400abank1fg676_iobs_0.v (4669, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_lfsr32_0.v (2047, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_main_0.v (5030, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_parameters_0.v (2286, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_ram8d_0.v (3622, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_rd_gray_cntr.v (2422, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_s3_dm_iob_0.v (1545, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_s3_dqs_iob.v (2657, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_s3_dq_iob.v (1991, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_tap_dly.v (6356, 2009-02-13)
ddr2_controller\ddr2_spartan3a1400abank1fg676_test_bench_0.v (7832, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_top_0.v (8499, 2009-05-18)
ddr2_controller\ddr2_spartan3a1400abank1fg676_wr_gray_cntr.v (2292, 2009-02-13)
ddr2_controller\ddr2_top.ucf (119169, 2009-05-20)
ddr2_controller\ddr2_top.v (5386, 2009-05-20)
ddr2_controller (0, 2010-02-23)

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