UART_Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：484KB
下载次数：21
上传日期：2010-03-06 19:05:31
上 传 者：
bobpark
说明： Altera FPGA的UART通讯程序
(Altera FPGA' s UART communication program)
文件列表:
uart_tb.v.bak (854, 2007-11-29)
uart_tb.vcd (3324924, 2007-11-29)
vsim.wlf (40960, 2007-11-29)
rtl_wrk\@rx\verilog.asm (13311, 2007-11-29)
rtl_wrk\@rx\_primary.dat (1519, 2007-11-29)
rtl_wrk\@rx\_primary.vhd (375, 2007-11-29)
rtl_wrk\@tx\verilog.asm (9378, 2007-11-29)
rtl_wrk\@tx\_primary.dat (1100, 2007-11-29)
rtl_wrk\@tx\_primary.vhd (419, 2007-11-29)
rtl_wrk\uart_tb\verilog.asm (7871, 2007-11-29)
rtl_wrk\uart_tb\_primary.dat (860, 2007-11-29)
rtl_wrk\uart_tb\_primary.vhd (134, 2007-11-29)
rtl_wrk\_info (534, 2007-11-29)
modelsim.ini (23274, 2007-11-29)
run.do (137, 2007-11-29)
Rx.v (3781, 2007-11-29)
Rx.v.bak (3780, 2007-11-29)
Tx.v (2801, 2007-11-29)
Tx.v.bak (2793, 2007-11-29)
uart_tb.v (848, 2007-11-29)
rtl_wrk\@rx (0, 2010-02-21)
rtl_wrk\@tx (0, 2010-02-21)
rtl_wrk\uart_tb (0, 2010-02-21)
rtl_wrk (0, 2010-02-21)
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