文件列表:

xge_mac(verilog 源码)\tags\initial\doc\xge_mac_spec.odt (130193, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\auto_verilog.sh (1741, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\custom.el (542, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\include\CRC32_D64.v (16408, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\include\CRC32_D8.v (4256, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\include\defines.v (4432, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\include\timescale.v (22, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\include\utils.v (3164, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\fault_sm.v (9199, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\generic_fifo.v (5987, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\generic_fifo_ctrl.v (7418, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\generic_mem_medium.v (5160, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\generic_mem_small.v (5160, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\meta_sync.v (3351, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\meta_sync_single.v (3715, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\rx_data_fifo.v (3938, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\rx_dequeue.v (6826, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\rx_enqueue.v (23766, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\rx_hold_fifo.v (3795, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\sync_clk_core.v (3649, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\sync_clk_wb.v (5946, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\sync_clk_xgmii_tx.v (4113, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\tx_data_fifo.v (4041, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\tx_dequeue.v (30049, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\tx_enqueue.v (6107, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\tx_hold_fifo.v (3957, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\wishbone_if.v (7207, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\rtl\verilog\xge_mac.v (24184, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\sim\systemc\compile.sh (804, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\sim\systemc\run.sh (18, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\sim\systemc\sc.mk (793, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\sim\systemc\verilator.cmd (155, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\sim\verilog\sim.do (2337, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\crc.cpp (1910, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\crc.h (584, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\sc_cpu_if.cpp (7835, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\sc_cpu_if.h (4479, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\sc_main.cpp (7589, 2008-06-01)
xge_mac(verilog 源码)\tags\initial\tbench\systemc\sc_packet.cpp (4879, 2008-06-01)
... ...

======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below. . |-- doc - Documentation files | |-- rtl | |-- include - Verilog defines and utils | `-- verilog - Verilog source files for xge_mac | |-- sim | |-- systemc - SystemC simulation directory | `-- verilog - Verilog simulation directory | `-- tbench |-- systemc - SystemC test-bench source files `-- verilog - Verilog test-bench source files ------------------------ 2. Simulation ------------------------ There are two simulation environments that can be used to validate the code. The verilog simulation is very basic and meant for those who want to look at how the MAC operates without going through the effort of setting up SystemC. The SystemC environment is more sophisticated and covers all features of the MAC. ------------------------ 2.1 Verilog Simulation ------------------------ To run the verilog simulation, compile all project files under rtl/verilog along with top level testbench file: - tbench/verilog/tb_xge_mac.v There is a Modelsim "do" file called "sim.do" under sim/verilog for those using Modelsim. Once all the files are compiled, start simulation using entity "tb". The verilog simulation reads packets from "packet_tx.txt" and writes them to the MAC transmit fifo using the packet transmit interface (pkt_tx_data). As frames become available in the transmit fifo, the MAC calulates the CRC and sends them out on xgmii_tx. The xgmii_tx interface is looped-back to xgmii_rx in the testbench. The frames are thus processed by the MAC receive engine and stored in the receive fifo. The testbench reads frames from the receive interface (pkt_rx_data) and prints out the results. ------------------------ 2.2 SystemC Simulation ------------------------ In order to use the SystemC environment it is required to first install SystemC from www.systemc.org. Free membership may be required to download the core SystemC files. The testbench was developed and tested with Verilator, a free HDL simulator that compiles verilog into C++ or SystemC code. You can download Verilator from www.veripool.org. You also need to install SystemPerl and Verilog-Perl for waveform traces. Once all the required tools are installed: - Move to directory sim/systemc - Type "./compile.sh" - Type "./run.sh" If the simulation is running correctly you should see messages from the scoreboard as packets are transmited and received on the various interfaces. Simulation output: ----------------------- Packet size ----------------------- SCOREBOARD XGMII INTERFACE TX (60) SCOREBOARD XGMII INTERFACE TX (60) SCOREBOARD PACKET INTERFACE TX (50) SCOREBOARD XGMII INTERFACE TX (60) SCOREBOARD PACKET INTERFACE TX (51) SCOREBOARD XGMII INTERFACE TX (60) SCOREBOARD PACKET INTERFACE RX (TX SIZE=60 RX SIZE=60) ...

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