文件列表:

sdram_vhd_134\brst_cntr.vhd (952, 2003-05-28)
sdram_vhd_134\cslt_cntr.vhd (1060, 2003-05-28)
sdram_vhd_134\functional_mti.do (791, 2003-06-14)
sdram_vhd_134\func_map_mti.do (328, 2002-05-14)
sdram_vhd_134\func_translate_mti.do (334, 2002-05-14)
sdram_vhd_134\ihdlutil.vhd (18068, 2002-03-23)
sdram_vhd_134\ki_cntr.vhd (1081, 2003-05-28)
sdram_vhd_134\micron (0, 2003-06-11)
sdram_vhd_134\micron\ed_comnd.vhd (6222, 2002-03-23)
sdram_vhd_134\micron\io_utils.vhd (8437, 2002-03-23)
sdram_vhd_134\micron\mt48lc1m16a1-8a.vhd (49526, 2002-03-23)
sdram_vhd_134\micron\mt48lc1m16a1.vhd (48748, 2002-03-23)
sdram_vhd_134\micron\mti_pkg.vhd (4638, 2002-03-23)
sdram_vhd_134\micron\stdlogar.vhd (66407, 2002-03-23)
sdram_vhd_134\micron\test.txt (3233, 2002-03-23)
sdram_vhd_134\micron\test.vhd (5973, 2002-03-23)
sdram_vhd_134\micron\util1164.vhd (3186, 2002-03-23)
sdram_vhd_134\micron\vec_gen.vhd (11284, 2002-03-23)
sdram_vhd_134\mti_pkg.vhd (4638, 2002-03-23)
sdram_vhd_134\rcd_cntr.vhd (1111, 2003-05-28)
sdram_vhd_134\ref_cntr.vhd (1027, 2003-05-28)
sdram_vhd_134\sdram_vhd_134.npl (3108, 2003-06-06)
sdram_vhd_134\sdrm.ucf (5304, 2002-08-09)
sdram_vhd_134\sdrm.vhd (16943, 2003-05-28)
sdram_vhd_134\sdrmc_state.vhd (5461, 2003-05-28)
sdram_vhd_134\sdrm_functional_tb.vhd (8328, 2003-06-04)
sdram_vhd_134\sdrm_t.vhd (7317, 2003-05-28)
sdram_vhd_134\sdrm_timing_tb.vhd (8298, 2002-03-23)
sdram_vhd_134\sys_int.vhd (7130, 2003-05-28)
sdram_vhd_134\timing_mti.do (331, 2002-03-28)
sdram_vhd_134\vrlgutil.vhd (4527, 2002-03-23)
sdram_vhd_134\wave_functional.do (551, 2003-06-14)
sdram_vhd_134\wave_timing.do (536, 2002-03-23)

-- Copyright(C) 2003 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. Design Description: The SDRAM controller is designed for a Virtex device. It's simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz. For a full functional description see Application Note 134: http://www.xilinx.com/xapp/xapp134.pdf Design Type: ISE (chip Virtex V300bg432-6) Design Hierarchy: sdrm (top level) sdrm_tb.vhd (Test Bench) sys_int (system interface) sdrm_t (SDRAM controller) sdrmc_state (state machine) brst_cntr (burst counter) rcd_cntr (ras-cas-delay counter) ref_cntr (refresh counter) cslt_cntr (cas-latency counter) ki_cntr (keep-idle-during-refresh-active counter) Simulation: Requires the following simulation libraries: Unisims Simprims The initial timing violations can be safely ignored. They are caused while the ram is being initialized. Warning: The File->Save Project As... operation of Project Navigator does not copy files Which are not actual project or source files. If this example is saved to a new location, the user should manually copy the following files to the new location. For synthesis: For Simulation: micron folder, wave_functional.do, and wave_timing.do files. Design Notes: - NOTE: Simplicity users still need to remove use std.textio.all in all vhd files - DLL: (in sdrm module) . dll0: use for clock mirror, provide the clock for the external SDRAM . dll1: use for deskewing clock signal inside the FPGA (Clk_j), also provide clk2x (Clk_i) - Use global clock buffers for clock signals: . There are 4 BUFGPs in Virtex. They provide low-skew high-fanout routings. - Use LUT Shift Register to delay signals by certain number of clock cycles . delay DLL lock signal (in sdrm_t module) . delay data (in sys_int module) - Registering all inputs and ouputs to SDRAM: (in sdrm module) . All signals going to the SDRAM are registered in the IOB This makes it easy to calculate timings b/t the FPGA and SDRAM For write cycles, add FPGA Tiockp to SDRAM Tsu For read cycles, add SDRAM Tac to FPGA Tsu and . The tristate signal for the data lines are also registered in the IOB . Instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. The tristate signal is sd_doe_n in sdrm - Use fast output buffers: (in sdrm module) . IOBUF_F_12: all signals interfacing to SDRAM These may create more bounce but are ~2ns faster than regular OBUFs - Use NODELAY mode for input buffers: (in ucf constraint file) . The default IBUF has additional delay to give negative hold time. This eliminates pad-to-pad hold time . Set NODELAY attribute on inputs to reduce IBUF delay by about 1.5ns - Set timing constraints for place & route tool: (in ucf constraint file) . set clock period on input clock (Clkp) . set periods b/t clk1x and clk2x (Clk_j, Clk_i) . set OFFSET constraint for inputs and outputs Frequently asked questions: 1. Is RAS to CAS delay programmable? . No, the data registers has a fixed number of pipeline stages. This reference design supports RAS-to-CAS delay of 2 clock cycles. If you need to adjust to a different RAS-to-CAS delay, change the SRL16 Address values in sys_int.v. The address value should be (Trcd/Tck) +1 . Note, you still need to write the RAS-to-CAS value to the Controller's Mode Reg during PRECHARGE command. The value should be (Trcd/Tck) -2 2. How do I modify the design to support 128Mb/256Mb SDRAM parts with a ***-bit data bus? . You'll need to add more IO buffers for the extra data and address signals (in sdrm.v) . You'll need to change ADDR_MSB and DATA_MSB (in define.v) . In the current design, instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. You may need to add 4 more tristate lines if you're going to ***-bit. The tristate signal is sd_doe_n in sdrm.v NOTE: If you are trying to run this example in a read-only location, the design hierachy will not display properly. Please copy the example project to a new location by using either Project Save As... from the File menu pulldown in ISE or some other method of your choice. Copy the example to a location where you have write permissions and the hiearchy will display properly. For support information and contacts please see: http://support.xilinx.com or http://support.xilinx.com/support/services/contact_info.htm

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