ref-ddr-sdram-vhdl
所属分类：VHDL/FPGA/Verilog
开发工具：Windows_Unix
文件大小：1007KB
下载次数：200
上传日期：2004-07-08 15:42:46
上 传 者：
baoshenghua
说明： 用VHDL编写DDR SDRAM Controller的源代码
( Compiles DDR SDRAM Controller with VHDL the source code )
文件列表:
doc (0, 2000-08-14)
doc\ddr_sdram.pdf (472801, 2000-05-30)
model (0, 2000-08-14)
model\mt46v4m16.vhd (43490, 1999-11-08)
model\mti_pkg.vhd (4932, 2000-08-14)
route (0, 2000-08-14)
route\ddr_sdram.csf (92655, 2001-04-11)
route\ddr_sdram.esf (732, 2001-04-11)
route\ddr_sdram.psf (2371, 2001-04-11)
route\ddr_sdram.quartus (193, 2000-08-14)
route\ddr_sdram.vqm (603177, 2000-06-30)
route\pll1.vhd (5081, 2000-06-29)
simulation (0, 2000-08-14)
simulation\APEX20KE_MF.VHD (42715, 2000-06-29)
simulation\ddr_command.vhd (17418, 2000-08-14)
simulation\ddr_control_interface.vhd (9161, 2000-08-14)
simulation\ddr_data_path.vhd (9286, 2000-08-14)
simulation\ddr_sdram.vhd (18307, 2000-08-14)
simulation\ddr_sdram_tb.vhd (24245, 2000-08-14)
simulation\io_utils.vhd (8703, 1998-01-16)
simulation\lpm_pack.vhd (22051, 1999-10-22)
simulation\modelsim.ini (8116, 2000-08-14)
simulation\mt46v4m16.vhd (43490, 1999-11-08)
simulation\mti_pkg.bak (4932, 1999-11-08)
simulation\mti_pkg.vhd (4932, 2000-08-14)
simulation\pll1.vhd (5081, 2000-06-29)
simulation\stdlogar.vhd (68654, 1998-01-16)
simulation\util1164.vhd (3310, 1998-01-16)
simulation\wave.do (5967, 2000-08-14)
simulation\work (0, 2000-08-14)
simulation\work\altcam (0, 2000-08-14)
simulation\work\altcam\behave.dat (7970, 2000-08-14)
simulation\work\altcam\behave.psm (69568, 2000-08-14)
simulation\work\altcam\_primary.dat (5972, 2000-08-14)
simulation\work\altclklock (0, 2000-08-14)
simulation\work\altclklock\behavior.dat (2016, 2000-08-14)
simulation\work\altclklock\behavior.psm (12360, 2000-08-14)
simulation\work\altclklock\_primary.dat (799, 2000-08-14)
... ...
File/Directory Description
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the vhdl SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the vhdl testbench, modelsim project file, and library
\source Contains the vhdl source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Version History
===============
v1.0 First release
v1.0.1 Updates to csf/esf/psf constraint files in \route to correct pin conflict on U3.
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