sdram_control
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3609KB
下载次数：30
上传日期：2010-03-18 14:19:58
上 传 者：
bigchop
说明： 基于XILINX FPGA的SDRAM 控制器代码。VERILOG HDL代码编写
(SDRAM CONTROLER)
文件列表:
sdram_control\src\Command.v (17532, 2005-06-18)
sdram_control\src\control_interface.v (8494, 2004-11-28)
sdram_control\src\datacnl.v.bak (8741, 2005-11-22)
sdram_control\src\Params.v (935, 2005-06-14)
sdram_control\src\sdram_test_tb.v.bak (8764, 2005-11-22)
sdram_control\src\sdr_data_path.v (2760, 2004-08-02)
sdram_control\src\sdr_sdram.v (7233, 2005-06-14)
sdram_control\src (0, 2005-12-09)
sdram_control\sim\altera_mf.v (1139393, 2004-11-28)
sdram_control\sim\mt48lc2m32b2.v (50092, 2004-09-03)
sdram_control\sim\Params.v (935, 2005-06-14)
sdram_control\sim\sdram_test.wlf (57344, 2005-11-22)
sdram_control\sim\sdram_test_tb.v (7746, 2005-11-22)
sdram_control\sim\sdram_test_tb.v.bak (7757, 2005-11-22)
sdram_control\sim\work\_info (13615, 2005-12-14)
sdram_control\sim\work\stx_scale_cntr\verilog.asm (14344, 2005-12-14)
sdram_control\sim\work\stx_scale_cntr\_primary.dat (1598, 2005-12-14)
sdram_control\sim\work\stx_scale_cntr\_primary.vhd (611, 2005-12-14)
sdram_control\sim\work\stx_scale_cntr (0, 2005-12-09)
sdram_control\sim\work\stx_n_cntr\verilog.asm (8453, 2005-12-14)
sdram_control\sim\work\stx_n_cntr\_primary.dat (840, 2005-12-14)
sdram_control\sim\work\stx_n_cntr\_primary.vhd (351, 2005-12-14)
sdram_control\sim\work\stx_n_cntr (0, 2005-12-09)
sdram_control\sim\work\stx_m_cntr\verilog.asm (8782, 2005-12-14)
sdram_control\sim\work\stx_m_cntr\_primary.dat (888, 2005-12-14)
sdram_control\sim\work\stx_m_cntr\_primary.vhd (414, 2005-12-14)
sdram_control\sim\work\stx_m_cntr (0, 2005-12-09)
sdram_control\sim\work\stratix_lvds_rx\verilog.asm (24186, 2005-12-14)
sdram_control\sim\work\stratix_lvds_rx\_primary.dat (1854, 2005-12-14)
sdram_control\sim\work\stratix_lvds_rx\_primary.vhd (625, 2005-12-14)
sdram_control\sim\work\stratix_lvds_rx (0, 2005-12-09)
sdram_control\sim\work\stratixii_tx_outclk\verilog.asm (15499, 2005-12-14)
sdram_control\sim\work\stratixii_tx_outclk\_primary.dat (1131, 2005-12-14)
sdram_control\sim\work\stratixii_tx_outclk\_primary.vhd (457, 2005-12-14)
sdram_control\sim\work\stratixii_tx_outclk (0, 2005-12-09)
sdram_control\sim\work\stratixii_lvds_rx\verilog.asm (98124, 2005-12-14)
sdram_control\sim\work\stratixii_lvds_rx\_primary.dat (6693, 2005-12-14)
sdram_control\sim\work\stratixii_lvds_rx\_primary.vhd (1078, 2005-12-14)
sdram_control\sim\work\stratixii_lvds_rx (0, 2005-12-09)
sdram_control\sim\work\stratixgx_dpa_lvds_rx\verilog.asm (117251, 2005-12-14)
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