说明：  ：ISE5.1i是Xilinx推出的具有ASIC-strength的设计工具，它充分发掘了VirtexⅡPro系列芯片的潜力；Virtex-II Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比，设计人员在编译时所花的时间得到了成倍提高（从100,000/min增加到200,000门/min）并且在器件速度上增加了40 。
(: ISE5.1i is a Xilinx introduced a ASIC-strength design tools, which fully exploit the Virtex Ⅱ Pro series chip' s potential Virtex-II Pro series of chip gate density of 40,000 to 8,000,000 from the door. Compared with the 4.1i, the designer at compile time, the time spent has been improved several times (from 100,000/min to 200,000 gate/min) and in the device speed increase of 40 .)