说明：  本文又用C语言实现了标准的自适应算术编码，拿它与用FPGA实现的改进后的自适应算术编码的仿真结果对比验证了这种改进后编码器编码的正确性。此种结构的编码效率很高，一个时钟编码一个数据比特，时钟频率可以达到50MHZ，占用的硬件资源大约有800个CLB(可配置逻辑模块)。
(This thesis realizes the adaptive arithmetic coding which is not improved with C language，compare with the result of simulation of improved adaptive arithmetic coder and indicates that the output of improved coder is correct．The frequency of clock Call reach up to 50M／s and it Call processes a data in one clock．It uses about 800 CLBs (Configurable logic block)．)