说明：  给出了一个利用格雷码对地址编码的羿步FIFO的实现方法，并给出了VHDL程序，以解决异步读写时钟引起的问题。为了解决FIFO的异步操作问题，本文提出了一种利用格雷码对地址进行编码的异步FIFO的设计，并采用VHDL语言进行电路设计，利用Altera公司 FLEX10KE系列FPGA得以实现，该电路软件仿真和硬件实现已经通过验证，并被应用到各种电路中。实践证明它可以解决由于异步产生的错误，同时增加了应用灵活性。
(Gives a Gray code using the address coding Yi-step implementation of FIFO method, and gives the VHDL program to address the problems caused by the asynchronous read and write clocks. In order to solve the operational problems of asynchronous FIFO, this paper presents a Gray code to encode the address of the asynchronous FIFO design and circuit design using VHDL language, using Altera' s FPGA realization FLEX10KE series, the circuit software simulation and hardware implementation has passed authentication, and is applied to a variety of circuits. Practice has proved that it can resolve the error generated due to asynchronous, while increasing application flexibility.)