FPGA
所属分类：通讯编程文档
开发工具：Visual C++
文件大小：1948KB
下载次数：4
上传日期：2010-03-28 11:01:12
上 传 者：
mousimin
说明： FPGA编程课程演示PPT，包括语法入门，语法进阶和实例分析。
(FPGA programming course presentation PPT, including Grammar, syntax and examples of advanced analysis.)
文件列表:
FPGA (0, 2009-11-11)
FPGA\verilog (0, 2009-11-11)
FPGA\verilog\1_060816185339 (0, 2009-11-11)
FPGA\verilog\1_060816185339\source (0, 2009-11-11)
FPGA\verilog\1_060816185339\source\chap10 (0, 2009-11-11)
FPGA\verilog\1_060816185339\source\chap10\acc.acf (14721, 2004-07-31)
FPGA\verilog\1_060816185339\source\chap10\acc.hif (1510, 2004-07-31)
FPGA\verilog\1_060816185339\source\chap10\acc.v (582, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\accn.v (273, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap10\add8.v (132, 2003-11-25)
FPGA\verilog\1_060816185339\source\chap10\adder8.v (313, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap10\block1.v (190, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\block2.v (191, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\block3.v (183, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\block4.v (191, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\control.v (1371, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap10\fsm.v (946, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap10\longframe1.v (327, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\longframe2.v (401, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\pipeline.v (872, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\reg8.v (214, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\resource1.v (227, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap10\resource2.v (319, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11 (0, 2009-11-11)
FPGA\verilog\1_060816185339\source\chap11\account.v (2068, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\clock.v (3602, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\count10.v (304, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\fre_ctrl.v (312, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap11\latch_16.v (155, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\paobiao.v (889, 2003-12-06)
FPGA\verilog\1_060816185339\source\chap11\sell.v (918, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\song.v (3265, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap11\traffic.v (1815, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap12 (0, 2009-11-11)
FPGA\verilog\1_060816185339\source\chap12\add_ahead.v (1060, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap12\add_bx.v (134, 2003-11-25)
FPGA\verilog\1_060816185339\source\chap12\add_jl.v (659, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap12\add_tree.v (942, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap12\correlator.v (1012, 2003-12-04)
FPGA\verilog\1_060816185339\source\chap12\crc.v (1906, 2003-12-04)
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