说明：  序列检测器的设计 一．实验目的 1. 掌握用VHDL 实现状态机的方法 2. 利用状态机设计一个序列检测器 二．实验内容 使用状态机设计一个5位序列检测器。从一串二进制码中检测出一个已预置的5位二进制码”10110” [具体要求] 1.画出状态转换图。（每增加一位二进制码相当于增加一个状态，再加上一个初始态，用6个状态可以实现.） 2.写出状态机的源程序，编译。要求当检测到预置序列时，输出一个脉冲的高电平，其余时候输出为低电平。 3.进行仿真，看结果是否正确。
(Sequence Detector Design 1. Purpose of the experiment 1. Control with VHDL state machine approach to achieve 2. Using the state machine to design a sequence detector 2. Experimental content Using the state machine to design a 5 sequence detector. From a string of binary code has been detected in a 5-bit binary preset code "10110" [Specific requirements] 1. Draw the state transition diagram. (Each additional is equivalent to a binary code to add a state, combined with an initial state, the state can be achieved with 6.) 2. Write state machine of the source, compile. Requests when it detects preset sequence, the output of a pulse of high, when the rest of the output is low. 3. Simulation to see the results are correct.)