文件列表:

VERILOG_BOOK_EXAMPLES (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPA (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\MUX.SPJ (138, 1995-11-09)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\MUX.V (964, 1995-10-28)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRI0.SPJ (173, 1995-11-09)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRI0.V (433, 1995-10-28)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRIREG.SPJ (181, 1995-11-09)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRIREG.V (442, 1995-10-12)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\WAND_WOR.SPJ (113, 1995-11-09)
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\WAND_WOR.V (428, 1995-10-28)
VERILOG_BOOK_EXAMPLES\APPB (0, 2004-03-09)
VERILOG_BOOK_EXAMPLES\APPC (0, 2004-03-09)
VERILOG_BOOK_EXAMPLES\APPD (0, 2004-03-09)
VERILOG_BOOK_EXAMPLES\APPE (0, 2004-03-09)
VERILOG_BOOK_EXAMPLES\APPF (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO\FIFO.SPJ (223, 2002-11-01)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO\FIFO.V (10181, 2002-11-01)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.SPJ (277, 1995-11-06)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.TIM (2623, 1995-10-12)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.V (4201, 1995-10-28)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\INI_FILE (44784, 1995-10-12)
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\TESTDRAM.V (9544, 1995-11-06)
VERILOG_BOOK_EXAMPLES\CHAP1 (0, 2004-03-09)
VERILOG_BOOK_EXAMPLES\CHAP10 (0, 2004-03-13)
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG (0, 2004-03-13)
... ...

**************************************************************** Examples from "Verilog HDL: A Guide to Digital Design and Synthesis", Second Edition by Samir Palnitkar Email: s_palnitkar@yahoo.com sspalnitkar@hotmail.com **************************************************************** Examples are provided for all chapters, wherever applicable. Each directory and sub-directory has a README.TXT file which explains the contents of that directory. Each chapter directory contains: chap_eg/ A directory that contains examples discussed in the chapter. exercise/ A directory that contains solutions to selected exercises. Instructions for Simulating Book Examples: ------------------------------------------ 1) The README.TXT files in each directory describe what each file in that sub-directory contains and also explains any special instructions for that file (e.g. the file is not simulatable or file is for synthesis, not simulation etc.). 2) Invoke the Silos 2001 Simulator. 3) To simulate an example, navigate to the appropriate chapter directory. A project file (.spj) corresponding to every Verilog (.v) file is created for you in each sub directory. You can simulate a Verilog (.v) file by simply opening the corresponding project file(.spj) file in the Silos 2001 simulator. When the project file(.spj) is open, click on the GO button. (Note: You may want to set up an association between .spj files and Silos 2001 program so that you can simply double click on a .spj file to bring up the Silos 2001 simulator). 4) To view the results, click-on the Open Analyzer(waveform) button. If a project (.spj) file is not present, it means that the file is for illustration purpose only and not for simulation purpose. 5) Refer to Silos 2001 Help for details on running the simulator.

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