verilog
所属分类：书籍源码
开发工具：VHDL
文件大小：19572KB
下载次数：125
上传日期：2010-04-01 00:06:19
上 传 者：
hopehit
说明： 大量verilog例程 详细具体 适合于初学者好好学习
(A large number of detailed and specific for verilog routine learn beginner)
文件列表:
Verilog HDL程序设计\Chapter-1\adder\adder.cr.mti (512, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\adder.mpf (16771, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\adder.v (201, 2007-08-03)
Verilog HDL程序设计\Chapter-1\adder\adder_testbench.do (870, 2007-08-15)
Verilog HDL程序设计\Chapter-1\adder\adder_testbench.v (549, 2007-08-03)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-3.bmp (586974, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-4.bmp (807726, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-5.bmp (630774, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-6.bmp (763926, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-7.bmp (676326, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\chart\图1-8.bmp (353958, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\transcript (389, 2007-12-17)
Verilog HDL程序设计\Chapter-1\adder\vsim.wlf (32768, 2007-08-15)
Verilog HDL程序设计\Chapter-1\adder\work\adder\transcript (389, 2007-12-17)
Verilog HDL程序设计\Chapter-1\adder\work\adder\verilog.txt.asm (2424, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\adder\_primary.dat (162, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\adder\_primary.vhd (258, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\adder_testbench\verilog.asm (6855, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\adder_testbench\_primary.dat (556, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\adder_testbench\_primary.vhd (90, 2007-08-18)
Verilog HDL程序设计\Chapter-1\adder\work\_info (340, 2007-08-18)
Verilog HDL程序设计\Chapter-10\10.2\chart\图10-12.bmp (439806, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\chart\图10-7.bmp (400374, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\chart\图10-8.bmp (420534, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\chart\图10-9.bmp (420534, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\csc.cr.mti (493, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\csc.mpf (16773, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\csc_testbench.v (2547, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\rgb2ycrcb.v (1173, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\transcript (495, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\vsim.wlf (6397952, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\wave\csc_testbench.bmp (1255554, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\wave\rgb2ycrcb.bmp (1747710, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\csc_testbench\verilog.asm (38637, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\csc_testbench\_primary.dat (3070, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\csc_testbench\_primary.vhd (314, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\rgb2ycrcb\verilog.asm (13458, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\rgb2ycrcb\_primary.dat (1483, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\rgb2ycrcb\_primary.vhd (552, 2007-08-21)
Verilog HDL程序设计\Chapter-10\10.2\work\_info (394, 2007-08-21)
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