文件列表:

vhdl\bitreg.vhd (1821, 2001-04-18)
vhdl\bytereg.vhd (1852, 2001-04-18)
vhdl\clk_div.vhd (5962, 2001-04-18)
vhdl\crcreg.vhd (3446, 2001-04-18)
vhdl\jcounter.vhd (2244, 2001-04-18)
vhdl\onewire_iface.vhd (8149, 2001-04-18)
vhdl\onewire_iface_syn.prj (1221, 2001-04-17)
vhdl\onewire_master.vhd (42213, 2001-04-18)
vhdl\shreg.vhd (3317, 2001-04-18)
vhdl\TEST_ONEWIRE_IFACE.DO (3133, 2001-04-18)
vhdl\TEST_ONEWIRE_IFACE.VHD (3707, 2001-04-18)
vhdl (0, 2001-04-18)
verilog\bitreg.v (2422, 2001-03-22)
verilog\clk_div.v (2480, 2001-03-22)
verilog\crcreg.v (2896, 2001-03-22)
verilog\defines.v (2823, 2001-03-22)
verilog\glbl.v (119, 1999-12-14)
verilog\jcnt1.v (1373, 2001-03-22)
verilog\jcnt2.v (1396, 2001-03-22)
verilog\onewire_iface.v (3797, 2001-04-18)
verilog\onewire_iface_syn.prj (1258, 2001-04-17)
verilog\onewire_master.v (34913, 2001-04-18)
verilog\parallel_sn_data.v (2942, 2001-04-18)
verilog\sr1.v (1398, 2001-03-15)
verilog\sr2.v (1379, 2001-03-15)
verilog\TEST_NO_SLAVE.do (574, 2001-03-21)
verilog\TEST_NO_SLAVE.v (677, 2001-03-22)
verilog\TEST_ONEWIRE_WITH_BAD_CRC.do (1166, 2001-03-22)
verilog\TEST_ONEWIRE_WITH_BAD_CRC.v (2198, 2001-03-22)
verilog\TEST_ONEWIRE_WITH_VALID_CRC.do (1132, 2001-03-22)
verilog\TEST_ONEWIRE_WITH_VALID_CRC.v (2166, 2001-03-22)
verilog\TEST_SLAVE_PRESENT.do (548, 2001-03-22)
verilog\TEST_SLAVE_PRESENT.v (864, 2001-03-22)
verilog (0, 2001-04-18)
xapp198[1].pdf (170536, 2010-04-06)

=========================================================================== README =================== Version: 1.0 Last Update: 04/18/2001 Xilinx. Inc. =========================================================================== ==================== Description ==================== This package contains the VHDL and Verilog source codes of the 1-wire interface design. ==================== Platform ==================== Windows NT 4.0 Synplify 6.0 ModelSim XE 5.3d ==================== Design Hierarchy ==================== onewire_iface (top level) clk_div (clock divider) onewire_master (state machine) shreg (shift register) jcounter (johnson counter) bitreg (bit register) bytereg (byte register) crcreg (crc generator) ==================== Instructions ==================== (1) use the vhdl source codes: . To run functional simulation with MTI: enter the vhdl directory (cd vhdl) do test_onewire_iface.do (or from the menu: Macro -> Execute Macro) wait for the MTI to simulate for 7 ms. . To compile the design with Synplify: open onewire_iface_syn.prj file click on the "run" button (2) use the verilog source codes: . To run functional simulation with MTI: enter the verilog directory (cd verilog) do TEST_ONEWIRE_WITH_VALID_CRC.do (or from the menu: Macro -> Execute Macro) Four test benches are available for different simulation purposes. . To compile the design with Synplify: open onewire_iface_syn.prj file click on the "run" button ==================== Files List ==================== vhdl: \vhdl shreg.vhd component bitreg.vhd component bytereg.vhd component jcounter.vhd component crcreg.vhd component clk_div.vhd component onewire_master.vhd main FSM design onewire_iface.vhd top level design onewire_iface_syn.prj Synplify project file for synthesis TEST_ONEWIRE_IFACE.VHD a simulation test bench TEST_ONEWIRE_IFACE.DO ModelSim Do file verilog: \verilog defines.v compile time options definition sr1.v component sr2.v component jcnt1.v component jcnt2.v component bitreg.v component parallel_sn_data.v component glbl.v component crcreg.v component clk_div.v component onewire_master.v main FSM design onewire_iface.v top level design onewire_iface_syn.prj Synplify project file for synthesis TEST_SLAVE_PRESENT.v a simulation test bench TEST_SLAVE_PRESENT.do ModelSim Do file TEST_ONEWIRE_WITH_VALID_CRC.v a simulation test bench TEST_ONEWIRE_WITH_VALID_CRC.do ModelSim Do file TEST_ONEWIRE_WITH_BAD_CRC.v a simulation test bench TEST_ONEWIRE_WITH_BAD_CRC.do ModelSim Do file TEST_NO_SLAVE.v a simulation test bench TEST_NO_SLAVE.do ModelSim Do file

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