DA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：15KB
下载次数：35
上传日期：2010-04-08 15:19:08
上 传 者：
chen2017chen
说明： 采用Verilog在FPGA上实现一阶Σ-Δ DAC，仿真和实际验证都正确，基本可以达到16位DAC的信噪比
(Using Verilog to implement the first sigma delta DAC on the FPGA, the simulation and practical verification are correct, basically can achieve 16 bit DAC signal-to-noise ratio)
文件列表:
DA\da (3632, 2009-07-13)
DA\da.c (1273, 2009-07-13)
DA\da.hex (386, 2009-07-13)
DA\da.lnp (52, 2009-07-13)
DA\da.LST (3301, 2009-07-13)
DA\da.M51 (6374, 2009-07-13)
DA\da.OBJ (3315, 2009-07-13)
DA\da.Opt (1760, 2009-07-13)
DA\da.Uv2 (2224, 2009-07-13)
DA\da_Opt.Bak (1758, 2009-07-11)
DA\da_Uv2.Bak (2225, 2009-07-11)
DA\STARTUP.A51 (6376, 2009-07-13)
DA\STARTUP.LST (10764, 2009-07-13)
DA\STARTUP.OBJ (750, 2009-07-13)
DA\新建 文本文档.txt (503, 2009-07-13)
DA (0, 2009-07-13)
DA\da.plg (15702, 2009-07-13)
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