说明：  本文档介绍了一个简单的单周期CPU，和流水线CPU的实现过程。 这是我们完成伯克利大学EECS系计算机系统结构课程的实验文档，实验信息见http://www-inst.eecs.berkeley.edu/~cs152/fa05/
(This document describes a simple single-cycle CPU, and CPU pipeline implementation process. This is the complete Berkeley EECS Department of the experimental computer architecture curriculum documents, test information, see http://www-inst.eecs.berkeley.edu/ ~ cs152/fa05 /)