74hc74
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：309KB
下载次数：118
上传日期：2010-04-19 18:48:13
上 传 者：
mypudn0001
说明： no intro
(With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.)
文件列表:
74hc74.pdf (194404, 2009-06-08)
74hc74 (0, 2009-06-08)
74hc74\component (0, 2009-06-08)
74hc74\constraint (0, 2009-06-08)
74hc74\coreconsole (0, 2009-06-08)
74hc74\designer (0, 2009-06-08)
74hc74\designer\impl1 (0, 2009-06-08)
74hc74\designer\impl1\designer.log (444, 2009-06-04)
74hc74\designer\impl1\d_ff.adb (29696, 2009-06-04)
74hc74\designer\impl1\d_ff.dtf (0, 2009-06-08)
74hc74\designer\impl1\d_ff.dtf\verify.log (233, 2009-06-04)
74hc74\designer\impl1\d_ff.ide_des (601, 2009-06-04)
74hc74\designer\impl1\d_ff.pdb (16896, 2009-06-04)
74hc74\designer\impl1\d_ff.pdb.depends (0, 2009-06-04)
74hc74\designer\impl1\d_ff.tcl (170, 2009-06-04)
74hc74\designer\impl1\d_ff_fp (0, 2009-06-08)
74hc74\designer\impl1\d_ff_fp\$$FlashPro_07294.L$$ (144, 2009-06-04)
74hc74\designer\impl1\d_ff_fp\d_ff.log (1209, 2009-06-04)
74hc74\designer\impl1\d_ff_fp\d_ff.pro (1568, 2009-06-08)
74hc74\designer\impl1\d_ff_fp\projectData (0, 2009-06-08)
74hc74\designer\impl1\d_ff_fp\projectData\d_ff.pdb (16896, 2009-06-04)
74hc74\designer\impl1\simulation (0, 2009-06-08)
74hc74\d_ff.prj (3599, 2009-06-08)
74hc74\hdl (0, 2009-06-08)
74hc74\hdl\d_ff.v (1910, 2009-06-04)
74hc74\phy_synthesis (0, 2009-06-08)
74hc74\simulation (0, 2009-06-08)
74hc74\simulation\modelsim.ini (262, 2009-06-08)
74hc74\simulation\modelsim.ini.sav (262, 2009-06-05)
74hc74\smartgen (0, 2009-06-08)
74hc74\smartgen\smartgen.aws (366, 2009-06-08)
74hc74\stimulus (0, 2009-06-08)
74hc74\synthesis (0, 2009-06-08)
74hc74\synthesis\backup (0, 2009-06-08)
74hc74\synthesis\backup\d_ff.srr (847, 2009-06-04)
74hc74\synthesis\coreip (0, 2009-06-08)
74hc74\synthesis\d_ff.areasrr (871, 2009-06-04)
74hc74\synthesis\d_ff.edn (7540, 2009-06-04)
74hc74\synthesis\d_ff.htm (320, 2009-06-08)
74hc74\synthesis\d_ff.map (28, 2009-06-04)
... ...
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