zonghe5
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：245KB
下载次数：7
上传日期：2010-04-25 10:37:00
上 传 者：
Master May
说明： 闹钟、电子钟典型实例，具有校时，整点报时等功能
(Alarm clock, electronic clock typical example, a school, the whole point of time and other functions)
文件列表:
zonghe5\clock.asm.rpt (8500, 2010-04-24)
zonghe5\clock.bsf (4212, 2010-04-22)
zonghe5\clock.done (26, 2010-04-24)
zonghe5\clock.fit.eqn (12767, 2010-04-24)
zonghe5\clock.fit.rpt (45803, 2010-04-24)
zonghe5\clock.fit.summary (382, 2010-04-24)
zonghe5\clock.flow.rpt (4042, 2010-04-24)
zonghe5\clock.map.eqn (11570, 2010-04-24)
zonghe5\clock.map.rpt (18141, 2010-04-24)
zonghe5\clock.map.summary (322, 2010-04-24)
zonghe5\clock.pin (19185, 2010-04-24)
zonghe5\clock.pof (212109, 2010-04-24)
zonghe5\clock.qpf (1557, 2010-04-24)
zonghe5\clock.qsf (2637, 2010-04-24)
zonghe5\clock.qws (1960, 2010-04-24)
zonghe5\clock.sim.rpt (4471, 2010-04-24)
zonghe5\clock.sof (57967, 2010-04-24)
zonghe5\clock.tan.rpt (58198, 2010-04-24)
zonghe5\clock.tan.summary (1357, 2010-04-24)
zonghe5\clock.vhd (2336, 2010-04-24)
zonghe5\clock.vwf (26203, 2010-04-24)
zonghe5\cmp_state.ini (2, 2010-04-24)
zonghe5\counter10.vhd (598, 2010-04-21)
zonghe5\counter24.vhd (693, 2010-04-21)
zonghe5\counter6.vhd (593, 2010-04-21)
zonghe5\db\add_sub_ilh.tdf (2756, 2010-04-24)
zonghe5\db\add_sub_jlh.tdf (2958, 2010-04-24)
zonghe5\db\add_sub_klh.tdf (3160, 2010-04-24)
zonghe5\db\clock.(0).cnf.cdb (2074, 2010-04-24)
zonghe5\db\clock.(0).cnf.hdb (1196, 2010-04-24)
zonghe5\db\clock.(1).cnf.cdb (1652, 2010-04-21)
zonghe5\db\clock.(1).cnf.hdb (559, 2010-04-21)
zonghe5\db\clock.(2).cnf.cdb (1497, 2010-04-21)
zonghe5\db\clock.(2).cnf.hdb (546, 2010-04-21)
zonghe5\db\clock.(3).cnf.cdb (898, 2010-04-24)
zonghe5\db\clock.(3).cnf.hdb (475, 2010-04-24)
zonghe5\db\clock.(4).cnf.cdb (2257, 2010-04-21)
zonghe5\db\clock.(4).cnf.hdb (545, 2010-04-21)
zonghe5\db\clock.(5).cnf.cdb (1108, 2010-04-21)
zonghe5\db\clock.(5).cnf.hdb (629, 2010-04-21)
... ...
近期下载者：
相关文件：
收藏者：