RAM
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：616KB
下载次数：8
上传日期：2010-04-26 11:40:38
上 传 者：
lynneangel
说明： 上述文件是一个ram的开发过程。。。次过程的程序都是我自己写的。验证结果正确。。。
(The file is a ram in the development process. . . Second process procedures are written in my own. Verification result is correct. . .)
文件列表:
RAM\ADD8B.bsf (1596, 2009-07-18)
RAM\ADD8B.vhd (491, 2009-07-18)
RAM\ADD8B.vhd.bak (483, 2009-07-18)
RAM\ADDRESS.bsf (1598, 2009-07-18)
RAM\ADDRESS.vhd (464, 2009-07-18)
RAM\ADDRESS.vhd.bak (497, 2009-07-18)
RAM\db\altsyncram_06q1.tdf (13035, 2009-07-19)
RAM\db\altsyncram_12e1.tdf (2979, 2009-07-18)
RAM\db\altsyncram_47r1.tdf (13067, 2009-07-18)
RAM\db\altsyncram_6h92.tdf (14003, 2009-07-18)
RAM\db\altsyncram_96c1.tdf (2958, 2009-07-18)
RAM\db\altsyncram_el72.tdf (13990, 2009-07-18)
RAM\db\altsyncram_nmf1.tdf (2998, 2009-07-18)
RAM\db\altsyncram_s5b2.tdf (14022, 2009-07-18)
RAM\db\decode_aoi.tdf (3435, 2009-07-18)
RAM\db\prev_cmp_testRAMWR.asm.qmsg (2190, 2009-07-19)
RAM\db\prev_cmp_testRAMWR.fit.qmsg (42817, 2009-07-19)
RAM\db\prev_cmp_testRAMWR.map.qmsg (14077, 2009-07-19)
RAM\db\prev_cmp_testRAMWR.qmsg (487112, 2009-07-19)
RAM\db\prev_cmp_testRAMWR.sim.qmsg (487112, 2009-07-19)
RAM\db\prev_cmp_testRAMWR.tan.qmsg (41705, 2009-07-19)
RAM\db\testRAMWR.db_info (152, 2009-11-13)
RAM\db\testRAMWR.eco.cdb (176, 2009-11-13)
RAM\db\testRAMWR.sim.cvwf (1813, 2009-07-19)
RAM\db\testRAMWR.sld_design_entry.sci (169, 2009-11-13)
RAM\db\wed.wsf (13046, 2009-07-19)
RAM\Delay.vhd (262, 2009-07-18)
RAM\Delay.vhd.bak (263, 2009-07-18)
RAM\DOUBLRAM.bsf (5466, 2009-07-18)
RAM\DOUBLRAM.cmp (1129, 2009-07-18)
RAM\DOUBLRAM.inc (926, 2009-07-18)
RAM\DOUBLRAM.qip (547, 2009-07-18)
RAM\DOUBLRAM.vhd (9913, 2009-07-18)
RAM\DOUBLRAM_inst.vhd (211, 2009-07-18)
RAM\DOUBLRAM_wave0.jpg (114436, 2009-07-18)
RAM\DOUBLRAM_wave1.jpg (153018, 2009-07-18)
RAM\DOUBLRAM_waveforms.html (1955, 2009-07-18)
RAM\FIFO.bsf (3300, 2009-07-19)
RAM\FIFO.cmp (1115, 2009-07-19)
RAM\FIFO.inc (918, 2009-07-19)
... ...
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