说明：  实现功能简述:verilog写的 本模块主要功能是产生一个确定时钟周期长度（最长为256个时钟周期）的脉冲信号，可以自己设定脉冲长度，输出的脉冲信号与时钟上升沿同步 脉冲宽度 = pulsewide + 1 时钟周期 输入一个启动信号后，可以产生一个固定时钟周期长度的脉冲信号，与启动信号的长短无关！脉冲宽度可调！
(Functional Description of the module to achieve the main function is to produce a certain clock cycle length (up to 256 clock cycles) of the pulse signal can be set for pulse length, the output pulse signal synchronous with the clock rising edge pulse width = pulsewide+ 1 clock cycle enter a start signal, can produce a fixed clock cycle, pulse length, the length of the signal has nothing to do with the start! Pulse width adjustable!)