ml505_mig_design
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9114KB
下载次数：168
上传日期：2010-05-13 02:39:04
上 传 者：
黑羽·X
说明： Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1
(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)
文件列表:
ml505_mig_design\mig_30.gise (941, 2009-04-29)
ml505_mig_design\mig_30.ise (10920, 2009-04-29)
ml505_mig_design\mig_30.veo (8954, 2009-04-29)
ml505_mig_design\mig_30.xco (1188, 2009-04-29)
ml505_mig_design\mig_30.xise (9891, 2009-04-29)
ml505_mig_design\mig_30\docs\adr_cntrl_timing.xls (15360, 2009-03-28)
ml505_mig_design\mig_30\docs\read_data_timing.xls (22528, 2009-03-28)
ml505_mig_design\mig_30\docs\ug086.pdf (13345139, 2009-03-28)
ml505_mig_design\mig_30\docs\write_data_timing.xls (16384, 2009-03-28)
ml505_mig_design\mig_30\docs\xapp858.url (125, 2009-03-28)
ml505_mig_design\mig_30\example_design\datasheet.txt (3806, 2009-04-29)
ml505_mig_design\mig_30\example_design\log.txt (6496, 2009-04-29)
ml505_mig_design\mig_30\example_design\mig.prj (2974, 2009-04-29)
ml505_mig_design\mig_30\example_design\par\chipscope.cpj (31341, 2009-05-04)
ml505_mig_design\mig_30\example_design\par\create_ise.bat (363, 2009-04-29)
ml505_mig_design\mig_30\example_design\par\icon.ngc (29108, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\icon.v (38965, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\icon.veo (1076, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\icon.xco (1323, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\icon4_cg.xco (1372, 2009-04-29)
ml505_mig_design\mig_30\example_design\par\icon_flist.txt (146, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\icon_xmdf.tcl (2467, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila.cdc (3735, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila.ngc (241455, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila.v (385798, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila.veo (1165, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila.xco (3716, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila_flist.txt (144, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ila_xmdf.tcl (2614, 2009-04-30)
ml505_mig_design\mig_30\example_design\par\ise_flow.bat (1162, 2009-04-29)
ml505_mig_design\mig_30\example_design\par\ise_flow_results.txt (610362, 2009-05-02)
ml505_mig_design\mig_30\example_design\par\mem_interface_top.ut (724, 2009-04-29)
ml505_mig_design\mig_30\example_design\par\mig_30.bit (1756654, 2009-05-02)
ml505_mig_design\mig_30\example_design\par\mig_30.bld (3988, 2009-05-02)
ml505_mig_design\mig_30\example_design\par\mig_30.pad (43330, 2009-05-02)
ml505_mig_design\mig_30\example_design\par\mig_30.par (32259, 2009-05-02)
ml505_mig_design\mig_30\example_design\par\mig_30.ucf (19397, 2009-04-30)
... ...
*******************************************************************************
** Copyright 2009, Xilinx, Inc.
** This design is confidential and proprietary of Xilinx, Inc. All Rights Reserved.
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/ Version: 3.0
** \ \ Filename: readme.txt
** / / Date Last Modified:
** /___/ /\ Date Created:
** \ \ / \
** \___\/\___\
**
** Device:
** Purpose:
** Reference:
**
*******************************************************************************
**
** Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
** provided to you "as is." Xilinx and its licensors make and you
** receive no warranties or conditions, express, implied,
** statutory or otherwise, and Xilinx specifically disclaims any
** implied warranties of merchantability, noninfringement, or
** fitness for a particular purpose. Xilinx does not warrant that
** the functions contained in these designs will meet your
** requirements, or that the operation of these designs will be
** uninterrupted or error free, or that defects in the Designs
** will be corrected. Furthermore, Xilinx does not warrant or
** make any representations regarding use or the results of the
** use of the designs in terms of correctness, accuracy,
** reliability, or otherwise.
**
** LIMITATION OF LIABILITY. In no event will Xilinx or its
** licensors be liable for any loss of data, lost profits, cost
** or procurement of substitute goods or services, or for any
** special, incidental, consequential, or indirect damages
** arising from the use or operation of the designs or
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** limitation shall apply notwithstanding the failure of the
** essential purpose of any limited remedies herein.
**
*******************************************************************************
ML50x Memory Interface Generator Design
---------------------------------------
This DDR2 design was generated with the MIG v2.3 and modified to work on an ML50x.
A ChipScope Pro ICON and ILA cores were added as well. The hardware "trips" when
a data error is detected.
The ML50x with a -1 speed grade FPGA will run the MIG DDR2 memory at 200 MHz.
With a -2 FPGA, the memory interface can be run at 266 MHz, the rated speed of
the SODIMM included with the ML50x.
ML50x refers to the ML505, ML506, and ML507 boards.
Hardware Setup:
---------------
A variable differential clock source can be connected to J10 and J11. If no
other clock source is available, the DDR2 clock can be generated by the ML50x
Diff Clk Out, J12 and J13.
SW6 Setting:
12345678
150 MHz: 11001010
200 MHz: 01001010
300 MHz: 10001010
J54 must be connected for the Diff Clk Out to operate.
More details on the Switch settings can be found in the ML50x User Guide:
http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf.
Initially, set the differential input clock to 200 MHz.
LEDs:
err1 = Data Error detected
gpio_led[0] = phy_init_done;
Software Setup:
---------------
Unzip the file, ml505_mig_design.zip to your C:\ drive. Download the bitstream:
C:\ml505_mig_design\mig_30\example_design\par\mig_30.bit
For the ML506 use ml506_mig_design.zip.
For the ML507 use ml507_mig_design.zip.
Operation:
----------
After downloading the bitstream, depress the CPU RST button. Three LEDs,
GPIO[0:2] should appear green after the reset. Increase the frequency by either
adjusting the clock source or the SW6 settings as described above. When an error is
detected by the MIG interface, the red error LED, will come on.
At higher frequencies, above the rated speed for the FPGA DDR2 interface, the reset
will clear the error LED and restore the green LEDs. As the frequency increases
even more beyond the rated design frequency, the design will become unstable and the
reset may fail to consistently reset the design. Continuing to increase the speed,
will cause the reset to not clear the red LED and eventually the DCM will lose its
lock. This is indicated by GPIO[0] going out.
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