p4_adder.tar
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3KB
下载次数:43
上传日期:2010-05-17 22:21:00
上 传 者:
whyHune
说明: 用vhdl实现的P4加法器,包括主要元件rca加法器,carry select adder,pg模块,并提供了一个测试文件,用modelsim测试通过
(P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been tested by modelsim)
文件列表:
carry_select.vhd (1507, 2009-05-14)
fa.vhd (535, 2009-05-14)
g.vhd (411, 2009-05-14)
lfsr.vhd (1030, 2009-05-14)
P4_adder.vhd (4127, 2009-06-04)
pg.vhd (483, 2009-05-21)
rca.vhd (1876, 2009-06-18)
tb_P4.vhd (2102, 2009-05-21)
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