verilog

所属分类:单片机开发
开发工具:VHDL
文件大小:1KB
下载次数:38
上传日期:2010-05-17 23:31:16
上 传 者gab1997
说明:  设计可以对两个运动员赛跑计时的秒表:(1)只有时钟(clk)和一个按键(key),每按一次,key是持续一个时钟周期的高电平脉冲 (2)秒表输出用0-59的整数表示 (3)key: (A)按一下key,开始计数; (B)第一个运动员到终点时第二下key,记住时间,继续计数; (C)二个运动员到时按第三下key,停止计数; (D)然后按第四下key,秒表输出第一个运动员到终点的时间,即按第二下key时记住的计数值; (E)按第五下key,秒表清0。
(Design of the two athletes running time of the stopwatch: (1) Only the clock (clk) and a button (key), each time, key is continuing a clock cycle, high pulse (2) stopwatch output with 0-59 integer that (3) key: (A) Click the key, start counting (B) When the first player to finish under the second key, remember the time, continue to count (C) two players to press the third Under the key, stop counting (D) and then by the fourth under the key, stopwatch output of the first athletes to the end of the time, that is, the next key by the second count when remembered (E) by the fifth under the key, stopwatch clear 0.)

文件列表:
verilog\v4watch.v (1206, 2009-12-25)
verilog\v4watch_tb.v (530, 2009-12-25)
verilog (0, 2010-05-17)

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