turbo_VHDL
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:151KB
下载次数:125
上传日期:2010-05-19 22:01:54
上 传 者:
skle
说明: Turbo码的VHDL描述,可以下载下来看看
(VHDL description of Turbo Codes)
文件列表:
turbo[1] (0, 2006-01-04)
turbo[1]\makeDist (416, 2005-06-14)
turbo[1]\src (0, 2006-01-04)
turbo[1]\src\vhdl (0, 2006-01-04)
turbo[1]\src\vhdl\abPermut_e.vhd (3513, 2005-06-14)
turbo[1]\src\vhdl\abPermut_synth.vhd (3467, 2005-06-14)
turbo[1]\src\vhdl\accDistSel_e.vhd (3212, 2005-06-14)
turbo[1]\src\vhdl\accDistSel_synth.vhd (4505, 2005-06-14)
turbo[1]\src\vhdl\accDist_e.vhd (3290, 2005-06-14)
turbo[1]\src\vhdl\accDist_synth.vhd (3768, 2005-06-14)
turbo[1]\src\vhdl\acs_e.vhd (4093, 2005-06-14)
turbo[1]\src\vhdl\acs_synth.vhd (5847, 2005-06-14)
turbo[1]\src\vhdl\adder_e.vhd (3123, 2005-06-14)
turbo[1]\src\vhdl\adder_synth.vhd (2983, 2005-06-14)
turbo[1]\src\vhdl\clkDiv_e.vhd (3097, 2005-06-14)
turbo[1]\src\vhdl\clkDiv_synth.vhd (3073, 2005-06-14)
turbo[1]\src\vhdl\clkrst_beh.vhd (2999, 2005-06-14)
turbo[1]\src\vhdl\clkrst_e.vhd (3109, 2005-06-14)
turbo[1]\src\vhdl\cmp2_e.vhd (3165, 2005-06-14)
turbo[1]\src\vhdl\cmp2_synth.vhd (2914, 2005-06-14)
turbo[1]\src\vhdl\cod2_e.vhd (3216, 2005-06-14)
turbo[1]\src\vhdl\cod2_synth.vhd (3456, 2005-06-14)
turbo[1]\src\vhdl\cod3_e.vhd (3044, 2005-06-14)
turbo[1]\src\vhdl\cod3_synth.vhd (3284, 2005-06-14)
turbo[1]\src\vhdl\coder_e.vhd (3265, 2005-06-14)
turbo[1]\src\vhdl\coder_synth.vhd (3292, 2005-06-14)
turbo[1]\src\vhdl\delayer_e.vhd (3296, 2005-06-14)
turbo[1]\src\vhdl\delayer_synth.vhd (3398, 2005-06-14)
turbo[1]\src\vhdl\distances_e.vhd (3561, 2005-06-14)
turbo[1]\src\vhdl\distances_synth.vhd (4128, 2005-06-14)
turbo[1]\src\vhdl\distance_e.vhd (3258, 2005-06-14)
turbo[1]\src\vhdl\distance_synth.vhd (2977, 2005-06-14)
turbo[1]\src\vhdl\extInf_e.vhd (3819, 2005-06-14)
turbo[1]\src\vhdl\extInf_synth.vhd (5263, 2005-06-14)
turbo[1]\src\vhdl\interleaver_e.vhd (3455, 2005-06-14)
turbo[1]\src\vhdl\interleaver_synth.vhd (7317, 2005-06-14)
turbo[1]\src\vhdl\iteration_e.vhd (5046, 2005-06-14)
turbo[1]\src\vhdl\iteration_synth.vhd (13826, 2005-06-14)
turbo[1]\src\vhdl\limiter_e.vhd (3998, 2005-06-14)
turbo[1]\src\vhdl\limiter_synth.vhd (4678, 2005-06-14)
... ...
######################################################################
#### ####
#### README.txt ####
#### ####
#### This file is part of the turbo decoder IP core project ####
#### http://www.opencores.org/projects/turbocodes/ ####
#### ####
#### Author(s): ####
#### - David Brochart(dbrochart@opencores.org) ####
#### ####
######################################################################
#### ####
#### Copyright (C) 2005 Authors ####
#### ####
#### This source file may be used and distributed without ####
#### restriction provided that this copyright statement is not ####
#### removed from the file and that any derivative work contains ####
#### the original copyright notice and the associated disclaimer. ####
#### ####
#### This source file is free software; you can redistribute it ####
#### and/or modify it under the terms of the GNU Lesser General ####
#### Public License as published by the Free Software Foundation; ####
#### either version 2.1 of the License, or (at your option) any ####
#### later version. ####
#### ####
#### This source is distributed in the hope that it will be ####
#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
#### PURPOSE. See the GNU Lesser General Public License for more ####
#### details. ####
#### ####
#### You should have received a copy of the GNU Lesser General ####
#### Public License along with this source; if not, download it ####
#### from http://www.opencores.org/lgpl.shtml ####
#### ####
######################################################################
Turbo Decoder Release 0.3
=========================
MAIN FEATURES
-------------
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
MyHDL MODEL
-----------
For help : python launchTurbo.py -help
For default execution : python launchTurbo.py
It writes the Bit Error Rate for each iteration into a file:
turbo0.txt <- BER before decoding
turbo1.txt <- BER for iteration #1
turbo2.txt <- BER for iteration #2
turbo3.txt <- BER for iteration #3
VHDL MODEL
----------
The top-level entity is "turboDec".
All the turbo decoder parameters are stored in the "turbopack.vhd" file.
You can modify:
- the code rate (RATE)
- the number of decoding iterations (IT)
- the interleaver frame size (FRSIZE)
- the trellis' length (TREL1_LEN and TREL2_LEN)
- the received decoder signal width (SIG_WIDTH)
- the extrinsic information signal width (Z_WIDTH)
- the accumulated distance signal width (ACC_DIST_WIDTH)
AUTHOR
------
David Brochart
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