文件列表:

FIFO1\FIFO1.BAT (351, 1992-05-06)
FIFO1\FIFO1.RPT (33329, 1992-05-06)
FIFO1\FIFO1.LCA (20243, 1992-05-06)
FIFO1\FIFO1.XNF (15205, 1992-05-06)
FIFO1\FIFO1.SCP (790, 1992-05-06)
FIFO1\SCH\FIFO1.1 (6500, 1992-05-06)
FIFO1\SCH\FIFO8X8.2 (5875, 1991-12-08)
FIFO1\SCH\ASYIN8.1 (3295, 1992-05-06)
FIFO1\SCH\ASYSIN8.1 (3905, 1992-05-06)
FIFO1\SCH\ASYOUT8.1 (3294, 1992-05-06)
FIFO1\SCH\ASYSOUT8.1 (3789, 1992-05-06)
FIFO1\SCH\FIFO8X8.1 (29061, 1992-05-06)
FIFO1\SCH\FIFO1A.1 (9042, 1992-05-06)
FIFO1\SYM\FIFO8X8.1 (1933, 1991-12-08)
FIFO1\SYM\ASYIN8.1 (1871, 1992-05-06)
FIFO1\SYM\ASYOUT8.1 (1875, 1992-05-06)
FIFO1\SYM\ASYSIN8.1 (1956, 1992-05-06)
FIFO1\SYM\ASYSOUT8.1 (1876, 1992-05-06)
FIFO1\WIR\FIFO1.1 (2678, 1992-05-06)
FIFO1\WIR\FIFO8X8.1 (7103, 1992-05-06)
FIFO1\WIR\FIFO8X8.2 (1319, 1992-05-06)
FIFO1\WIR\ASYIN8.1 (2148, 1992-05-06)
FIFO1\WIR\ASYSIN8.1 (2661, 1992-05-06)
FIFO1\WIR\ASYSOUT8.1 (2629, 1992-05-06)
FIFO1\WIR\ASYOUT8.1 (2160, 1992-05-06)
FIFO1\WIR\FIFO1A.1 (4255, 1992-05-06)
FIFO2\FIFO2.BAT (497, 1992-05-06)
FIFO2\FIFO2.CST (1678, 1991-12-07)
FIFO2\FIFO2.RPT (31843, 1992-05-06)
FIFO2\FIFO2.LCA (20303, 1992-05-06)
FIFO2\FIFO2.XNF (55693, 1992-05-06)
FIFO2\FIFO2.SCP (6207, 1992-05-06)
FIFO2\SCH\FIFO2.1 (6544, 1992-05-06)
FIFO2\SCH\FIFO8X8.1 (19163, 1991-12-08)
FIFO2\SCH\FIFO8X8.2 (3204, 1992-05-06)
FIFO2\SCH\SR_SE2.1 (2292, 1991-12-08)
FIFO2\SCH\FIFO2A.1 (9041, 1992-05-06)
FIFO2\SCH\ASYIN8.1 (3295, 1992-05-06)
FIFO2\SCH\ASYSIN8.1 (3905, 1992-05-06)
... ...

_______________________________________________________________________ | | | XILINX APPLICATIONS NOTE XAPP005V V1.10 WH-5-6-92 | |_______________________________________________________________________| README file for the XC3000 register-based FIFO1 and FIFO2: ========================================================== Note: A more detailed description of this application can be obtained from XILINX Applications, phone 800-255-7778 (outside California), 408-879-5199, Fax 408-559-7114. Files included in XAPP005V.ZIP: ------------------------------- README This Readme file FIFO1\ This directory contains the 24 MHz 8x8 FIFO FIFO2\ This directory contains the 28 MHz 8x8 FIFO FIFO1 ----- This 8x8 FIFO uses the CE pin of CLBs to enable shifting of data inside of the register matrix. Therefore, the FIFO core will use 32 CLBs organized in a 8 columns by 4 rows CLB matrix. The control circuitry uses one CLB per word. The FIFO will internally run at approx. 24 MHz in a -150 LCA device, and at 20 MHz in a -125 device. Design files included in directory FIFO1: SCH\FIFO1.1 Top-level Viewlogic V4.0 schematic SCH\FIFO1A.1 Top-level schematic with Input and Output Synchronizers SCH\FIFO8X8.1 8 by 8 Fifo with control logic (Sheet 1) SCH\FIFO8X8.2 CLBMAPs for the 8 by 8 Fifo (Sheet 2) SCH\ASYIN8.1 Asynchronous input stage, edge triggered SCH\ASYSIN8.1 Asynchronous input stage (see below) SCH\ASYOUT8.1 Asynchronous output stage, edge triggered SCH\ASYSOUT8.1 Asynchronous output stage (see below) SYM\*.1 Viewlogic Symbols for FIFO and I/O Stages WIR\*.1 Viewlogic Wire files FIFO1.BAT Sample batch file for automatic design translation *.XNF Xilinx Netlists FIFO1.LCA Placed and routed LCA file FIFO1.RPT Report file FIFO1.SCP Schematics constraints file Software Versions used: DS390 Version 4.01 Viewlogic and Interface Viewdraw-LCA V4.0d WIR2XNF 4.01 Interface to Viewlogic XACT ADI Version 3.20 The schematic files are compatible with Viewlogic 4.1. To convert them to 4.1 files, load and save all schematics. Implementation Hints: The critical path in the control circuitry of the FIFO is detemined by the delay from POP to the clock enable of the first column of flip-flops. The XNFMAP 3.20 partitioner groups two bits of one word into the same CLB because of the naming of the bits (Q0_0 and Q0_1, Q0_2 and Q0_3). Both registers in one CLB can use the same CLB CE pin. Because the CE pin is used, APR 3.20 automatically lines up the registers in columns. The speed of the FIFO could be further increased by handplacing the control CLBs on the bottom of the FIFO such that a minimum of interconnect delay is introduced into the critical path. The nets in the critical path are: FIFO8X8/VALID and POP FIFO8X8/SE_6 FIFO8X8/SE_4 FIFO8X8/SE_2 FIFO8X8/RDY. The FIFO uses CLBMAPs to densely pack the logic of the control circuitry into CLBs. Longline and net criticality flags are added to increase the speed. The word width of the FIFO core can easily be changed by copying one or more rows and adding them on to the core. The naming of the new row(s) is important if register grouping and regular layout is desired. The depth of the FIFO can be changed by adding/deleting of columns. The following is the hierarchical design flow suggested by Xilinx: wir2xnf -x -p3020PC68-150 fifo8x8 wir2xnf -x -p3020PC68-150 fifo1 xnfmerge -p3020PC68-150 fifo1.xnf fifo1.xnf xnfdrc -p3020PC68-150 fifo1.xnf xnfmap -p3020PC68-150 fifo1.xnf map2lca -a -p3020PC68-150 fifo1.map apr -w -n -f fifo1.lca fifo1.lca makebits -o fifo1.bit -w -j -a fifo1.lca lca2xnf -h fifo1 fifo1s xnf2wir fifo1s vsm fifo1s Full timing simulation using Viewsim can now be performed. Note 1: Place and Route CPU time was <2 min. on a 486-25. There are four additional functional blocks included: 1.ASYIN8 is a asynchronous input stage for an 8-bit wide FIFO. It allows a word to be written into the FIFO with an asynchronous input clock. RDY signals that the FIFO is ready to receive a new word. Note, that IOB flip-flops could possibly be used to implement the data holding register if the data comes from off-chip. 2.ASYOUT8 is an asynchronous output stage for an 8-bit wide FIFO. It allows a word to be read from the FIFO with an asynchronous output clock. OUTRDY signals that the FIFO has a new word available. Note, that IOB flip-flops possibly could be used to implement the holding register for the data if the data goes off-chip. 3.ASYSIN8 is an asynchronous input stage for an 8-bit wide FIFO. It allows data to be written into the FIFO from a system that is not synchronized to the FIFO's internal clock. RDY signals that the FIFO is ready to receive a new word. 4.ASYSOUT8 is is an asynchronous output stage for an 8-bit wide FIFO. It allows a word to be written from the FIFO to a system that is not synchronized to the FIFO's internal clock. OUTRDY signals that the FIFO has a new word available. The schematic FIFO1A shows how to connect the input/output stages to the FIFO core. Performance: To analyze the internal performance, XDELAY -ANALYZE was used. The XDELAY reports for -150, -125, -100, and -70 parts are shown below. _______________________________________________________________________ XDelay: FIFO1.LCA (3020PC68-150), XDELAY 4.20, Wed May 6 10:55:27 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 41.7ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (EC) at "FIFO8X8/Q0_7.EC" Minimum Clock Period : 41.7ns Estimated Maximum Clock Speed : 24.0Mhz _______________________________________________________________________ XDelay: FIFO1.LCA (3020PC68-125), XDELAY 4.20, Wed May 6 10:54:20 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 48.7ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (EC) at "FIFO8X8/Q0_7.EC" Minimum Clock Period : 48.7ns Estimated Maximum Clock Speed : 20.5Mhz _______________________________________________________________________ XDelay: FIFO1.LCA (3020PC68-100), XDELAY 4.20, Wed May 6 10:56:50 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 58.8ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (EC) at "FIFO8X8/Q0_7.EC" Minimum Clock Period : 58.8ns Estimated Maximum Clock Speed : 17.0Mhz ______________________________________________________________________ XDelay: FIFO1.LCA (3020PC68-70), XDELAY 4.20, Wed May 6 10:57:10 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 74.6ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (EC) at "FIFO8X8/Q0_7.EC" Minimum Clock Period : 74.6ns Estimated Maximum Clock Speed : 13.4Mhz ====================================================================== FIFO2 ----- Compared with FIFO1, this implementation of the logic results in a higher speed at the same CLB count of the FIFO design. The implementation is somewhat more difficult, but shows how to take advantage of the LCA architecture as well as advanced software tools. This 8x8 FIFO does not use CLB CE pins. Therefore, the FIFO core can use 32 CLBs organized in a 4 columns by 8 rows CLB matrix. The advantage is a gain in speed because the critical path of the FIFO now can be implementad in adjacent CLBs with no interconnect delay. The control circuitry uses one CLB per word. Design files included in directory FIFO2: SCH\FIFO2.1 Top-level Viewlogic schematic SCH\FIFO2A.1 Top-level schematic with Input and Output Synchronizers SCH\FIFO8X8.1 8 by 8 Fifo with control logic (Sheet 1) SCH\FIFO8X8.2 CLBMAPs for the 8 by 8 Fifo (Sheet 2) SCH\SR_CE2.1 2-Bit S/R with non-shared CE in one CLB SCH\ASYIN8.1 Asynchronous input stage, edge triggered SCH\ASYSIN8.1 Asynchronous input stage (see below) SCH\ASYOUT8.1 Asynchronous output stage, edge triggered SCH\ASYSOUT8.1 Asynchronous output stage (see below) SYM\*.1 Viewlogic Symbols for FIFO and I/O stages WIR\*.1 Viewlogic Wire files FIFO2.BAT Batch file for automatic design translation *.XNF Xilinx Netlists FIFO2.CST Constraints file to lock CLBs in place. FIFO2.LCA Placed and routed LCA file FIFO2.RPT Report file FIFO1.SCP Schematics constraints file Software Versions used: DS390 Version 4.01 Viewlogic and Interface Viewdraw-LCA V4.0d WIR2XNF 4.01 Interface to Viewlogic XACT ADI Version 3.20 The schematic files are compatible with Viewlogic 4.1. To convert them to 4.1 files, load and save all schematics. Implementation Hints: The critical path in the control circuitry of the FIFO can be implemented in adjacent CLBs using zero delay interconnect. Therefore, the FIFO speed for an 8-word FIFO is approx. 28 MHz in a -150 part. The XNFMAP 3.20 partitioner groups two bits of one word into the same CLB because of a CLBMAP in the macro SR_SE2. CLB PINLOCK flags force the APR router to access longlines. The flip-flops in a XC3000 CLB share the CE pin. The register grouping does not allow this pin to be used, since in the design each register is enabled individually. Grouping two bits of adjacent words will result in a "tall and skinny" FIFO with optimally organized control logic. The critical path internal interconnect delays are reduced. APR does not recognize the structure of the design. Therefore, the placement and routing may not be regular. Without placement of the CLBs, the design speed may be as low as in the FIFO1. To achieve the highest performance, all blocks have to be locked manually in place and, because of deficiencies of the router, the critical path in the control logic sometimes has to be routed by hand. The nets in the critical path are: FIFO8X8/VALID FIFO8X8/SE_6 FIFO8X8/SE_4 FIFO8X8/SE_2 FIFO8X8/RDY. The FIFO2.CST file shows how to lock the FIFO elements in a pre-defined location: place block fifo8x8/q0_1 aa; place block fifo8x8/q1_1 ba; place block fifo8x8/q2_1 ca; place block fifo8x8/q3_1 da; . . . To move the FIFO, editing of this file is required. APR invoked with the -c options will read in a constraints file: APR -c fifo2.cst The FIFO uses CLBMAPs to densely pack the logic of the control circuitry into CLBs. Longline and net criticality flags are added to increase the speed. The word width of the FIFO core can easily be changed by copying one or more rows, and adding them to the core. The depth of the FIFO can be changed by adding/deleting of columns. The following is the hierarchical design flow suggested by Xilinx: wir2xnf -x -p3030PC68-150 sr_se2 wir2xnf -x -p3030PC68-150 fifo8x8 xnfmerge -p3030PC68-150 fifo8x8.xnf fifo8x8.xnf wir2xnf -x -p3030PC68-150 fifo2 xnfmerge -p3030PC68-150 fifo2.xnf fifo2.xnf xnfdrc -p3030PC68-150 fifo2.xnf xnfmap -p3030PC68-150 fifo2.xnf map2lca -a -p3030PC68-150 fifo2.map apr -w -n -f -c fifo2.cst fifo2.lca fifo2.lca makebits -o fifo2.bit -w -j -a fifo2.lca lca2xnf -h fifo2 fifo2s xnf2wir fifo2s vsm fifo2s Full timing simulation using Viewsim can now be performed. Note 1: The warnings 335 and 368 issued by XNFMAP can be ignored. Note 2: Place and Route CPU time was <2 min. on a 486-25. There are four additional functional blocks included: 1.ASYIN8 is a asynchronous input stage for an 8-bit wide FIFO. It allows a word to be written into the FIFO with an asynchronous input clock. RDY signals that the FIFO is ready to receive a new word. Note, that IOB flip-flops could possibly be used to implement the data holding register if the data comes from off-chip. 2.ASYOUT8 is an asynchronous output stage for an 8-bit wide FIFO. It allows a word to be read from the FIFO with an asynchronous output clock. OUTRDY signals that the FIFO has a new word available. Note, that IOB flip-flops possibly could be used to implement the holding register for the data if the data goes off-chip. 3.ASYSIN8 is an asynchronous input stage for an 8-bit wide FIFO. It allows data to be written into the FIFO from a system that is not synchronized to the FIFO's internal clock. RDY signals that the FIFO is ready to receive a new word. 4.ASYSOUT8 is is an asynchronous output stage for an 8-bit wide FIFO. It allows a word to be written from the FIFO to a system that is not synchronized to the FIFO's internal clock. OUTRDY signals that the FIFO has a new word available. The schematic FIFO2A shows how to connect the input/output stages to the FIFO core. Performance: To analyze the internal performance, XDELAY -ANALYZE was used. The XDELAY reports for -150, -125, -100, and -70 parts are shown below. _______________________________________________________________________ XDelay: FIFO2.LCA (3030PC68-150), XDELAY 4.20, Wed May 6 13:53:55 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 35.9ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (Din) at "FIFO8X8/Q1_1.B" Target FFY drives its own Din Target FFY drives Din to FFX driving net "FIFO8X8/Q1_1" Minimum Clock Period : 35.9ns Estimated Maximum Clock Speed : 27.8Mhz _______________________________________________________________________ XDelay: FIFO2.LCA (3030PC68-125), XDELAY 4.20, Wed May 6 13:54:14 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 40.8ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (Din) at "FIFO8X8/Q1_1.B" Target FFY drives its own Din Target FFY drives Din to FFX driving net "FIFO8X8/Q1_1" Minimum Clock Period : 40.8ns Estimated Maximum Clock Speed : 24.5Mhz _______________________________________________________________________ XDelay: FIFO2.LCA (3030PC68-100), XDELAY 4.20, Wed May 6 13:54:30 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 50.2ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (Din) at "FIFO8X8/Q1_1.B" Target FFY drives its own Din Target FFY drives Din to FFX driving net "FIFO8X8/Q1_1" Minimum Clock Period : 50.2ns Estimated Maximum Clock Speed : 19.9Mhz ______________________________________________________________________ XDelay: FIFO2.LCA (3030PC68-70), XDELAY 4.20, Wed May 6 13:54:45 1992 Xdelay timing analysis options: From all. To all. Output is limited to "Clock to Setup" paths. Clock net "CLK" path delays: Clock to Setup (same edge) : 62.4ns (4 block levels) Clock to Q, net "FIFO8X8/PSH_7" to FF Setup (Din) at "FIFO8X8/Q1_1.B" Target FFY drives its own Din Target FFY drives Din to FFX driving net "FIFO8X8/Q1_1" Minimum Clock Period : 62.4ns Estimated Maximum Clock Speed : 16.0Mhz --------------------------------- EOF --------------------------------

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