Verilog_HDL

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:159KB
下载次数:2
上传日期:2010-05-27 18:18:50
上 传 者ka0123
说明:  在微型计算机系统中,CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同 时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线;而串行通信中数据一位一位顺序传 送,能节省传送线.用Vefilog HDL语言实现了串并、并串通信接口之间的转换
(In the micro-computer systems, CPU basic communication with the outside there are two types of parallel data communication that you transmit at the same time, the advantage of faster transfer speeds, but the data how many how many transmission lines needed and the data in a serial communication send an order, to save transmission lines. With Vefilog HDL language to implement string and and the conversion between the serial communication interface)

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用Verilog+HDL语言实现并串、串并接口的转换.pdf (167767, 2010-05-19)

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