ddr_verilog_xilinx
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：128KB
下载次数：366
上传日期：2005-10-24 19:52:29
上 传 者：
vghost
说明： DDR（双速率）SDRAM控制器参考设计，xilinx提供
(DDR (double data rate) SDRAM controller reference design for Xilinx)
文件列表:
ddr_verilog_xilinx\top.ucf (3126, 2001-01-04)
ddr_verilog_xilinx\define.v (1677, 2000-12-08)
ddr_verilog_xilinx\glbl.v (109, 2000-10-02)
ddr_verilog_xilinx\mt46v4m16.v (46857, 2000-12-29)
ddr_verilog_xilinx\string_decode_fn.v (6858, 2001-01-04)
ddr_verilog_xilinx\tb_top.v (8248, 2001-01-12)
ddr_verilog_xilinx\top_func.v (45438, 2001-01-12)
ddr_verilog_xilinx\ddr_xilinx_使用说明.pdf (157689, 2005-10-24)
ddr_verilog_xilinx (0, 2005-10-24)
***********************ReadMe for XAPP253*********************
Contents of xapp253.zip file
contains verilog source files
*top.v* is the source file for DDR SDRAM controller
*tb_top.v* is the source file for testbench
*define.v* contains variable definitions
*mt46v4m16.v* is the simulation model of ***MB DDR SDRAM from Micron
*top.ucf* is the user constraint file to be specified during
Place and Route. This contains the constraints for 133MHz implementation
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