fir_filter
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：14KB
下载次数：17
上传日期：2010-06-01 15:12:02
上 传 者：
winnie_688
说明： 采用vhdl语言在Altera的开发板DE2-70上实现的低通滤波器的工程
(Vhdl language used in the Altera DE2-70 development board to achieve the low-pass filter project)
文件列表:
fir_filter\acc.v (1955, 2007-07-07)
fir_filter\accum.bsf (2256, 2007-07-07)
fir_filter\accum.v (4365, 2007-07-07)
fir_filter\filtref.bdf (13980, 2007-07-07)
fir_filter\filtref.qsf (3096, 2007-09-07)
fir_filter\fir.vwf (10490, 2007-07-07)
fir_filter\fir_filter.qpf (906, 2007-09-07)
fir_filter\hvalues.v (1634, 2007-07-07)
fir_filter\mult.bsf (2193, 2007-07-07)
fir_filter\mult.v (4407, 2007-07-07)
fir_filter\state_m.v (2662, 2007-07-07)
fir_filter\taps.v (2054, 2007-07-07)
fir_filter (0, 2009-11-06)
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