文件列表:

RD1030_71LVDS_demo\Documents (0, 2009-10-01)
RD1030_71LVDS_demo\Documents\rd1030.pdf (749621, 2009-09-25)
RD1030_71LVDS_demo\ecp2 (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\docs (0, 2009-03-31)
RD1030_71LVDS_demo\ecp2\verilog\par (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\par\loopback_par.lpf (2678, 2008-05-23)
RD1030_71LVDS_demo\ecp2\verilog\par\loopback_par.tcl (6721, 2008-05-22)
RD1030_71LVDS_demo\ecp2\verilog\par\loopback_par_tsim.tcl (6947, 2008-05-22)
RD1030_71LVDS_demo\ecp2\verilog\par\video_par.lpf (2757, 2008-05-27)
RD1030_71LVDS_demo\ecp2\verilog\par\Video_par.tcl (6550, 2008-05-22)
RD1030_71LVDS_demo\ecp2\verilog\par\video_par_tsim.tcl (6776, 2008-05-22)
RD1030_71LVDS_demo\ecp2\verilog\simulation (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\rtl (0, 2009-03-31)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\scripts (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\scripts\loopback_fsim.tcl (1479, 2008-04-29)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\scripts\loopback_tsim.tcl (755, 2008-04-29)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\scripts\video_fsim.tcl (3024, 2008-05-27)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\scripts\video_tsim.tcl (720, 2008-04-29)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\timing (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\simulation\modelsim\timing\video_wave.do (4214, 2008-04-22)
RD1030_71LVDS_demo\ecp2\verilog\source (0, 2009-10-01)
RD1030_71LVDS_demo\ecp2\verilog\source\addsub8.v (1532, 2007-08-17)
RD1030_71LVDS_demo\ecp2\verilog\source\Add_8.v (1135, 2007-08-17)
RD1030_71LVDS_demo\ecp2\verilog\source\align_word.v (3725, 2008-04-23)
RD1030_71LVDS_demo\ecp2\verilog\source\asm.bat (25, 2007-03-14)
RD1030_71LVDS_demo\ecp2\verilog\source\bit_align_ctl.v (11273, 2008-04-23)
RD1030_71LVDS_demo\ecp2\verilog\source\bit_align_ctl_sim.v (11345, 2008-05-13)
RD1030_71LVDS_demo\ecp2\verilog\source\CBHS.v (14154, 2007-08-24)
RD1030_71LVDS_demo\ecp2\verilog\source\CBHS_adj.v (8785, 2007-05-01)
RD1030_71LVDS_demo\ecp2\verilog\source\Char_Gen.mem (10238, 2007-03-22)
RD1030_71LVDS_demo\ecp2\verilog\source\Char_Gen.v (29542, 2007-08-17)
RD1030_71LVDS_demo\ecp2\verilog\source\CSC1.v (11568, 2007-05-01)
RD1030_71LVDS_demo\ecp2\verilog\source\CSC2.v (10247, 2007-05-01)
RD1030_71LVDS_demo\ecp2\verilog\source\deserializer.v (4507, 2008-04-23)
RD1030_71LVDS_demo\ecp2\verilog\source\deserializer_fsm.v (7506, 2008-05-15)
RD1030_71LVDS_demo\ecp2\verilog\source\dpram16x8.v (1749, 2007-08-17)
RD1030_71LVDS_demo\ecp2\verilog\source\dpram32x8.v (3087, 2007-05-01)
... ...

7:1 LVDS Video Interface Reference Design ============================================================ ---------------------------------------------------- Design Example 1: Loopback Test File List 1. /ReadMe.txt --> Read me file 2. /docs/*.* --> Documents 3. /par/loopback_par.tcl --> Script for running place and route /par/loopback_par_tsim.tcl --> Script for running place and route used only for timing simulation /par/loopback_par.lpf --> Constraint file for place and route 4. /simulation/modelsim/scripts/loopback_fsim.tcl --> Scripts for RTL simulation using Modelsim /simulation/modelsim/scripts/loopback_tsim.tcl --> Scripts for timing simulation using Modelsim 5. /source/*.vhd --> Source files 6. /synthesis/loopback_syn.tcl --> Scripts for synthesis using Synplify /synthesis/loopback_syn_tsim.tcl --> Scripts for synthesis using Synplify used only for timing simulation 7. /testbench/Loopback_Demo_7_to_1_LVDS_TOP_TB.vhd --> Testbench for simulation Function Simulation 1. Launch ModelSim Lattice edition 2. Click [File] -> [Change Directory...] and select "/simulation/modelsim/scripts" 3. Click [Tools] -> [TCL] -> [Excute Macro] select "/simulation/modelsim/scripts/loopback_fsim.tcl" Synthesis 1. Launch Synplify 2. Click [Run] -> [Run Tcl Scripts] and select /synthesis/loopback_syn.tcl (or loopback_syn_tsim.tcl for timing simulation) Place and Route a. Manual PAR 1. Launch ispLEVER 2. Create a new project in "/par" and name it loopback_demo_7_to_1_lvds_top (or loopback_demo_7_to_1_lvds_top_tsim for timing simulation), select EDIF type 3. Select device: Device Family: XP2 Device Name : LFXP2_17E Speed Grade : 5 Package Type : F484C 4. Import source file from "/synthesis/rev_1/loopback_71lvds.edn" (or loopback_71lvds_tsim.edn for timing simulation) 5. Import constraint file from "/par/loopback_par.lpf" 6. Run "Report Summary - HTML" for utilization, "Place and Route TRACE Report" for performance check or "Generate Timing Simulation Files" for timing simulation b. Run PAR using a script 1. Launch ispLEVER Tcl Editor 2. Open /RD1030/par/loopback_par.tcl (or loopback_par_tsim.tcl for timing simulation) 3. Change variable "set version" to the version of ispLEVER your are using, for example: if ispLEVER v6.1 is used, change it to "set version "6.1"" if ispLEVER v7.0 is used, change it to "set version "7.0"" 4. Change variable "proj_dir" to your working directory, for example: if the working directory is "D:\RD1030\xp2\vhdl\par", change it to "set proj_dir "D:/RD1030/xp2/vhdl/par"" 5. Select [Run] -> [Start] Timing Simulation 1. Launch Modelsim Lattice edition 2. Click [File] -> [Change Directory...] and select "/simulation/modelsim/scripts" 3. Click [Tools] -> [Excute Macro] select "/simulation/modelsim/scripts/loopback_tsim.tcl" and remember to do synthesis and place and route first. ---------------------------------------------------- Design Example 2: Demonstration of 7:1 LVDS Interface with Video Processing Functions File List 1. /ReadMe.txt --> Read me file 2. /docs/*.* --> Documents 3. /par/video_par.tcl --> Script for running place and route /par/video_par_tsim.tcl --> Script for running place and route used only for timing simulation /par/video_par.lpf --> Constraint file for place and route 4. /simulation/modelsim/scripts/video_fsim.tcl --> Scripts for RTL simulation using Modelsim /simulation/modelsim/scripts/video_tsim.tcl --> Scripts for timing simulation using Modelsim /simulation/modelsim/timing/video_wave.do --> Waveform do file for timing simulation using Modelsim 5. /source/*.vhd --> Source files 6. /synthesis/video_syn.tcl --> Scripts for synthesis using Synplify /synthesis/video_syn_tsim.tcl --> Scripts for synthesis using Synplify used only for timing simulation 7. /testbench/Video_Demo_7_to_1_LVDS_TOP_RTL_tb.vhd --> Testbench for RTL simulation /testbench/Video_Demo_7_to_1_LVDS_TOP_gate_tb.vhd --> Testbench for timing simulation Function Simulation 1. Launch ModelSim Lattice edition 2. Click [File] -> [Change Directory...] and select "/simulation/modelsim/scripts" 3. Click [Tools] -> [TCL] -> [Excute Macro] select "/simulation/modelsim/scripts/video_fsim.tcl" Synthesis 1. Launch Synplify 2. Click [Run] -> [Run Tcl Scripts] and select /synthesis/video_syn.tcl (or video_syn_tsim.tcl for timing simulation) Place and Route a. Manual PAR 1. Launch ispLEVER 2. Create a new project in "/par" and name it video_demo_7_to_1_lvds_top (or video_demo_7_to_1_lvds_top_tsim for timing simulation), select EDIF type 3. Select device: Device Family: XP2 Device Name : LFXP2_17E Speed Grade : 6 Package Type : F484C 4. Import source file from "/synthesis/rev_1/video_71lvds.edn" (or video_71lvds_tsim.edn for timing simulation) 5. Import constraint file from "/par/video_par.lpf" 6. Run "Report Summary - HTML" for utilization, "Place and Route TRACE Report" for performance check or "Generate Timing Simulation Files" for timing simulation b. Run PAR using a script 1. Launch ispLEVER Tcl Editor 2. Open /RD1030/par/video_par.tcl (or video_par_tsim.tcl for timing simulation) 3. Change variable "set version" to the version of ispLEVER your are using, for example: if ispLEVER v6.1 is used, change it to "set version "6.1"" if ispLEVER v7.0 is used, change it to "set version "7.0"" 4. Change variable "proj_dir" to your working directory, for example: if the working directory is "D:\RD1030\xp2\vhdl\par", change it to "set proj_dir "D:/RD1030/xp2/vhdl/par"" 5. Select [Run] -> [Start] Timing Simulation 1. Launch Modelsim Lattice edition 2. Click [File] -> [Change Directory...] and select "/simulation/modelsim/scripts" 3. Click [Tools] -> [Excute Macro] select "/simulation/modelsim/scripts/video_tsim.tcl" and remember to do synthesis and place and route first.

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：