mult

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1091KB
下载次数:55
上传日期:2010-06-05 18:28:52
上 传 者thesunofchina
说明:  16位乘法器,输入16位乘数,输出32位积,采用循环移位算法
(a multplier)

文件列表:
mult\.lso (6, 2010-06-03)
mult\coregen.cgp (520, 2010-06-01)
mult\coregen.log (0, 2010-06-01)
mult\coregen.rsp (273, 2010-06-01)
mult\d.ant (4077, 2010-05-30)
mult\d.jhd (41, 2010-05-30)
mult\d.tbw (596, 2010-05-30)
mult\d.xwv (19820, 2010-05-30)
mult\d.xwv_bak (19820, 2010-05-30)
mult\d_beh.prj (42, 2010-06-03)
mult\d_bencher.prj (23, 2010-05-30)
mult\d_isim_beh.exe (569518, 2010-06-03)
mult\d_isim_beh.wfs (460, 2010-06-03)
mult\isim\temp\hdllib.ref (130, 2010-06-03)
mult\isim\temp\hdpdeps.ref (338, 2010-06-03)
mult\isim\temp\sub00\vhpl00.vho (1074, 2010-06-03)
mult\isim\temp\sub00\vhpl01.vho (2786, 2010-06-03)
mult\isim\work\d\mingw\testbench_arch.obj (24804, 2010-06-03)
mult\isim\work\d\testbench_arch.h (1018, 2010-06-03)
mult\isim\work\d\xsimtestbench_arch.cpp (2076, 2010-06-03)
mult\isim\work\hdllib.ref (867, 2010-06-03)
mult\isim\work\hdpdeps.ref (2443, 2010-06-03)
mult\isim\work\m\mingw\testbench_arch.obj (24804, 2010-06-03)
mult\isim\work\m\testbench_arch.h (1018, 2010-06-03)
mult\isim\work\m\xsimtestbench_arch.cpp (3048, 2010-06-03)
mult\isim\work\mult2\behavioral.h (951, 2010-06-03)
mult\isim\work\mult2\mingw\behavioral.obj (10298, 2010-06-03)
mult\isim\work\mult3\behavioral.h (951, 2010-06-03)
mult\isim\work\mult3\mingw\behavioral.obj (23972, 2010-06-03)
mult\isim\work\mult3\xsimbehavioral.cpp (1831, 2010-06-03)
mult\isim\work\mult4\mingw\mult4_a.obj (15238, 2010-06-03)
mult\isim\work\mult4\mult4_a.h (933, 2010-06-03)
mult\isim\work\sub00\vhpl00.vho (1063, 2010-06-03)
mult\isim\work\sub00\vhpl01.vho (1157, 2010-06-03)
mult\isim\work\sub00\vhpl02.vho (576, 2010-06-03)
mult\isim\work\sub00\vhpl03.vho (3113, 2010-06-03)
mult\isim\work\sub00\vhpl04.vho (1064, 2010-06-03)
mult\isim\work\sub00\vhpl05.vho (2771, 2010-06-03)
mult\isim\work\sub00\vhpl06.vho (576, 2010-06-03)
mult\isim\work\sub00\vhpl07.vho (3115, 2010-06-03)
... ...

The following files were generated for 'mult1' in directory D:\code\mult: mult1.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. mult1.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. mult1.sym: Please see the core data sheet. mult1.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. mult1.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. mult1.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. mult1.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. mult1.xco: CORE Generator input file containing the parameters used to regenerate a core. mult1_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. mult1_readme.txt: Text file indicating the files generated and how they are used. mult1_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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