embedded_risc
所属分类：处理器开发
开发工具：Others
文件大小：125KB
下载次数：188
上传日期：2005-11-02 10:20:27
上 传 者：
qianqianx
说明： 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。
(an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.)
文件列表:
embedded_risc\CVS\Root (57, 2005-09-21)
embedded_risc\CVS\Repository (15, 2005-09-21)
embedded_risc\CVS\Template (0, 2005-09-21)
embedded_risc\CVS\Entries.Old (137, 2005-09-21)
embedded_risc\CVS\Entries (116, 2005-09-21)
embedded_risc\CVS\Entries.Extra.Old (107, 2005-09-21)
embedded_risc\CVS\Entries.Extra (86, 2005-09-21)
embedded_risc\CVS (0, 2005-09-21)
embedded_risc\SOC_Design.pdf (70922, 2002-06-06)
embedded_risc\Machine_Language\CVS\Root (57, 2005-09-21)
embedded_risc\Machine_Language\CVS\Repository (32, 2005-09-21)
embedded_risc\Machine_Language\CVS\Template (0, 2005-09-21)
embedded_risc\Machine_Language\CVS\Entries.Old (0, 2005-09-21)
embedded_risc\Machine_Language\CVS\Entries (48, 2005-09-21)
embedded_risc\Machine_Language\CVS\Entries.Extra.Old (0, 2005-09-21)
embedded_risc\Machine_Language\CVS\Entries.Extra (18, 2005-09-21)
embedded_risc\Machine_Language\CVS (0, 2005-09-21)
embedded_risc\Machine_Language\program.txt (7034, 2002-06-06)
embedded_risc\Machine_Language (0, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Root (57, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Repository (34, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Template (0, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Entries.Old (0, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Entries (52, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Entries.Extra.Old (0, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS\Entries.Extra (22, 2005-09-21)
embedded_risc\Test_Bench_Verilog\CVS (0, 2005-09-21)
embedded_risc\Test_Bench_Verilog\Top_level_tb.tf (5454, 2002-06-06)
embedded_risc\Test_Bench_Verilog (0, 2005-09-21)
embedded_risc\Verilog\CVS\Root (57, 2005-09-21)
embedded_risc\Verilog\CVS\Repository (23, 2005-09-21)
embedded_risc\Verilog\CVS\Template (0, 2005-09-21)
embedded_risc\Verilog\CVS\Entries.Old (0, 2005-09-21)
embedded_risc\Verilog\CVS\Entries (2178, 2005-09-21)
embedded_risc\Verilog\CVS\Entries.Extra.Old (0, 2005-09-21)
embedded_risc\Verilog\CVS\Entries.Extra (906, 2005-09-21)
embedded_risc\Verilog\CVS (0, 2005-09-21)
embedded_risc\Verilog\ACC.V (2148, 2002-06-06)
embedded_risc\Verilog\ALU.V (4598, 2002-06-06)
embedded_risc\Verilog\CONTROL.V (18978, 2002-06-06)
... ...
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