shift_regeister
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：145KB
下载次数：76
上传日期：2010-06-21 23:04:36
上 传 者：
gh5023
说明： 用blockram实现移位寄存器，开发语言为verilog hdl
(Shift register with blockram achieve the development language for the verilog hdl)
文件列表:
sim\testbench\tb.v (2315, 2010-05-03)
sim\testbench\clk_rst_gen.v (1073, 2010-04-17)
sim\testbench\glbl.v (1172, 2006-12-02)
sim\cic.do (575, 2010-05-03)
sim\work\_info (914, 2010-05-03)
sim\work\clk_rst_gen\_primary.vhd (329, 2010-05-03)
sim\work\clk_rst_gen\verilog.asm (4908, 2010-05-03)
sim\work\clk_rst_gen\_primary.dat (463, 2010-05-03)
sim\work\tb\_primary.vhd (64, 2010-05-03)
sim\work\tb\verilog.asm (6664, 2010-05-03)
sim\work\tb\_primary.dat (1210, 2010-05-03)
sim\work\dpram_block\_primary.vhd (568, 2010-05-03)
sim\work\dpram_block\verilog.asm (11400, 2010-05-03)
sim\work\dpram_block\_primary.dat (824, 2010-05-03)
sim\work\shift_reg_module\_primary.vhd (593, 2010-05-03)
sim\work\shift_reg_module\verilog.asm (29631, 2010-05-03)
sim\work\shift_reg_module\_primary.dat (5016, 2010-05-03)
sim\work\glbl\_primary.vhd (172, 2010-05-03)
sim\work\glbl\verilog.asm (8862, 2010-05-03)
sim\work\glbl\_primary.dat (1093, 2010-05-03)
sim\qq.mpf (30559, 2010-05-03)
sim\qq.cr.mti (2, 2010-05-03)
用blockram实现移位寄存器.doc (264704, 2010-05-03)
src\shift_reg_module.v (7889, 2010-05-03)
src\dpram_block.v (2624, 2010-04-05)
sim\work\_temp (0, 2010-05-03)
sim\work\clk_rst_gen (0, 2010-05-03)
sim\work\tb (0, 2010-05-03)
sim\work\dpram_block (0, 2010-05-03)
sim\work\shift_reg_module (0, 2010-05-03)
sim\work\glbl (0, 2010-05-03)
sim\testbench (0, 2010-05-03)
sim\work (0, 2010-05-03)
sim (0, 2010-05-03)
src (0, 2010-05-03)
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