f_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：443KB
下载次数：3
上传日期：2010-06-22 14:07:19
上 传 者：
ruiyang2010
说明： tsten通过对clk二分频，实现一秒钟的门脉冲，使被测频率通过，在这一秒钟内，通过计数器计数，实现频率的测定。
(tsten half by clk frequency, achieving a second gate pulse to the measured frequency is, at this very moment, through the counter counts, the determination of frequency.)
文件列表:
lab2\CNT10.bsf (2145, 2010-04-09)
lab2\cnt10.vwf (4600, 2010-04-09)
lab2\FTEST.bdf (18747, 2010-04-21)
lab2\FTEST.vwf (15212, 2010-04-29)
lab2\lan.cdf (287, 2010-04-09)
lab2\lan.done (26, 2010-04-29)
lab2\lan.dpf (239, 2010-04-09)
lab2\lan.fit.smsg (513, 2010-04-29)
lab2\lan.fit.summary (588, 2010-04-29)
lab2\lan.map.summary (450, 2010-04-29)
lab2\lan.pin (20470, 2010-04-29)
lab2\lan.pof (524474, 2010-04-29)
lab2\lan.qpf (904, 2010-04-09)
lab2\lan.qsf (4547, 2010-04-29)
lab2\lan.sof (151050, 2010-04-29)
lab2\lan.tan.summary (1585, 2010-04-29)
lab2\REG32B.bsf (1793, 2010-04-09)
lab2\REG32B.vhd (437, 2010-04-09)
lab2\REG32B.vwf (27983, 2010-04-09)
lab2\TESTCTL.bsf (1968, 2010-04-09)
lab2\TESTCTL.vhd (872, 2010-04-09)
lab2\TESTCTL.vwf (2731, 2010-04-29)
lab2\lan_assignment_defaults.qdf (37880, 2010-04-21)
lab2\CNT10.vhd.bak (1036, 2010-04-09)
lab2\CNT10.vhd (1036, 2010-04-22)
lab2\Thumbs.db (8192, 2010-05-28)
lab2\lan.qws (2385, 2010-04-30)
lab2\lan.sim.rpt (42613, 2010-04-29)
lab2\频率计波形.png (4716, 2010-04-29)
lab2\测频控制器波形.png (6356, 2010-04-29)
lab2\lan.map.rpt (20380, 2010-04-29)
lab2\lan.fit.rpt (94857, 2010-04-29)
lab2\lan.asm.rpt (8041, 2010-04-29)
lab2\lan.tan.rpt (77833, 2010-04-29)
lab2\lan.flow.rpt (6365, 2010-04-29)
lab2\db\lan.sim.cvwf (1496, 2010-04-29)
lab2\db\prev_cmp_lan.sim.qmsg (3362, 2010-04-29)
lab2\db\lan.sld_design_entry.sci (154, 2010-04-30)
lab2\db\prev_cmp_lan.qmsg (3362, 2010-04-29)
lab2\db\lan.eco.cdb (161, 2010-04-30)
... ...
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