VHDL_clock
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：70KB
下载次数：48
上传日期：2010-06-22 14:59:54
上 传 者：
pingguoxiong
说明： VHDL数字钟设计程序 设计要求 基本要求： 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）；-
(VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -)
文件列表:
Vhdl2.vhd.bak (2196, 2009-05-24)
Block1.bdf (6076, 2009-05-24)
count12.vhd (3311, 2009-05-24)
count12.vhd.bak (3282, 2009-05-24)
counter2.bsf (2121, 2009-05-24)
counter12.bsf (2514, 2009-05-21)
counter60.bsf (2514, 2009-05-21)
counter60.vhd (3152, 2009-05-21)
counter60.vhd.bak (3150, 2009-05-21)
shizhong.asm.rpt (7645, 2009-05-24)
shizhong.bdf (16224, 2009-05-24)
shizhong.db_import.rpt (2613, 2009-05-21)
shizhong.done (26, 2009-05-24)
shizhong.dpf (292, 2009-05-24)
shizhong.eda.rpt (4274, 2009-05-24)
shizhong.fit.rpt (115822, 2009-05-24)
shizhong.fit.smsg (411, 2009-05-24)
shizhong.fit.summary (409, 2009-05-24)
shizhong.flow.rpt (7456, 2009-05-24)
shizhong.map.rpt (22445, 2009-05-24)
shizhong.map.summary (410, 2009-05-24)
shizhong.pin (31130, 2009-05-24)
shizhong.pof (524473, 2009-05-24)
shizhong.qpf (907, 2009-05-21)
shizhong.qsf (4396, 2009-05-24)
shizhong.qws (1704, 2009-05-25)
shizhong.sdc (1184, 2009-05-21)
shizhong.sim.rpt (20423, 2009-05-24)
shizhong.sof (140504, 2009-05-24)
shizhong.sta.rpt (24604, 2009-05-21)
shizhong.sta.summary (331, 2009-05-21)
shizhong.tan.rpt (153167, 2009-05-24)
shizhong.tan.summary (1881, 2009-05-24)
shizhong.vwf (14073, 2009-05-24)
shizhong_nativelink_simulation.rpt (1670, 2009-05-21)
undo_redo.txt (162, 2009-05-24)
Vhdl2.vhd (2193, 2009-05-24)
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