VLSI_CA1.tar
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：144KB
下载次数：2
上传日期：2010-06-22 17:14:19
上 传 者：
mynewmeteora
说明： this is the implementaion of an 8-bit mirror adder in Verilog
文件列表:
VLSI_CA1 (0, 2010-04-18)
VLSI_CA1\p1_a (0, 2010-04-11)
VLSI_CA1\p1_a\schematic (0, 2010-04-11)
VLSI_CA1\p1_a\schematic\master.tag (36, 2010-04-10)
VLSI_CA1\p1_a\schematic\pc.db (104, 2010-04-10)
VLSI_CA1\p1_a\schematic\sch.cd% (3241, 2010-04-10)
VLSI_CA1\p1_a\schematic\sch.cd- (3241, 2009-04-29)
VLSI_CA1\p1_a\schematic\sch.cdb (3241, 2010-04-10)
VLSI_CA1\p1_a\schematic\prop.xx (524, 2010-04-10)
VLSI_CA1\p1_a\layout (0, 2010-04-12)
VLSI_CA1\p1_a\layout\master.tag (39, 2010-04-10)
VLSI_CA1\p1_a\layout\pc.db (56, 2010-04-10)
VLSI_CA1\p1_a\layout\layout.cd% (1786, 2010-04-10)
VLSI_CA1\p1_a\layout\layout.cdb (2518, 2010-04-10)
VLSI_CA1\p1_a\av_extracted (0, 2009-06-07)
VLSI_CA1\p1_a\av_extracted\master.tag (39, 2010-04-11)
VLSI_CA1\p1_a\av_extracted\pc.db (136, 2010-04-11)
VLSI_CA1\p1_a\av_extracted\layout.cdb (5368, 2010-04-11)
VLSI_CA1\p1_a\av_extracted\prop.xx (408, 2010-04-11)
VLSI_CA1\p1_a\symbol (0, 2010-04-10)
VLSI_CA1\p1_a\symbol\master.tag (39, 2010-04-10)
VLSI_CA1\p1_a\symbol\pc.db (0, 2010-04-10)
VLSI_CA1\p1_a\symbol\symbol.cd% (1382, 2010-04-10)
VLSI_CA1\p1_a\symbol\symbol.cdb (1424, 2010-04-10)
VLSI_CA1\p1_a\prop.xx (3500, 2010-04-10)
VLSI_CA1\p1_d (0, 2009-04-29)
VLSI_CA1\p1_d\schematic (0, 2009-04-29)
VLSI_CA1\p1_d\schematic\master.tag (36, 2009-04-29)
VLSI_CA1\p1_d\schematic\pc.db (179, 2009-04-29)
VLSI_CA1\p1_d\schematic\sch.cd% (5425, 2009-04-29)
VLSI_CA1\p1_d\schematic\sch.cdb (5390, 2009-04-29)
VLSI_CA1\p1_d\schematic\prop.xx (764, 2009-04-29)
VLSI_CA1\p1_e (0, 2009-04-29)
VLSI_CA1\p1_e\schematic (0, 2009-04-29)
VLSI_CA1\p1_e\schematic\master.tag (36, 2009-04-29)
VLSI_CA1\p1_e\schematic\pc.db (151, 2009-04-29)
VLSI_CA1\p1_e\schematic\sch.cd% (3499, 2009-04-29)
VLSI_CA1\p1_e\schematic\sch.cdb (3499, 2009-04-29)
VLSI_CA1\p1_e\schematic\prop.xx (764, 2009-04-29)
VLSI_CA1\p1_f (0, 2009-04-29)
... ...
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